u-boot.git/arch/arm/cpu, branch v2018.07

Merge branch 'master' of git://git.denx.de/u-boot-sunxi

2018-07-04T03:09:34Z

arm: timer: sunxi: add Allwinner timer erratum workaround

2018-07-03T16:30:00Z

The Allwinner A64 SoCs suffers from an arch timer implementation erratum, where sometimes the lower 11 bits of the counter value erroneously become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and backwards, with the latter one often showing weird behaviour. Port the workaround proposed for Linux to U-Boot and activate it for all A64 boards. This fixes crashes when accessing MMC devices (SD cards), caused by a recent change to actually use the counter value for timeout checks. Fixes: 5ff8e54888e4d26a352453564f7f599d29696dc9 ("sunxi: improve throughput in the sunxi_mmc driver") [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html Signed-off-by: Andre Przywara Reviewed-by: Philipp Tomsich Tested-by: Jagan Teki Tested-by: Andreas Färber Tested-by: Guillaume Gardet

arm: timer: factor out FSL arch timer erratum workaround

2018-07-03T16:29:46Z

At the moment we have the workaround for the Freescale arch timer erratum A-008585 merged into the generic timer_read_counter() routine. Split those two up, so that we can add other errata workaround more easily. Also add an explaining comment on the way. Signed-off-by: Andre Przywara Tested-by: Jagan Teki Tested-by: Andreas Färber Tested-by: Guillaume Gardet

ARM: Introduce ability to enable invalidate of BTB with ICIALLU on Cortex-A15 for CVE-2017-5715

2018-06-29T15:30:39Z

As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to be done unconditionally for Cortex-A15 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html Cc: Marc Zyngier Cc: Russell King Cc: Tony Lindgren Cc: Robin Murphy Cc: Florian Fainelli Cc: Catalin Marinas Cc: Will Deacon Cc: Christoffer Dall Cc: Andre Przywara Cc: Ard Biesheuvel Cc: Tom Rini Cc: Michael Nazzareno Trimarchi Signed-off-by: Nishanth Menon Tested-by: Fabio Estevam

ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715

2018-06-29T15:30:39Z

As recommended by Arm in [1], IBE[2] has to be enabled unconditionally for BPIALL to be functional on Cortex-A8 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html Cc: Marc Zyngier Cc: Russell King Cc: Tony Lindgren Cc: Robin Murphy Cc: Florian Fainelli Cc: Catalin Marinas Cc: Will Deacon Cc: Christoffer Dall Cc: Andre Przywara Cc: Ard Biesheuvel Cc: Tom Rini Cc: Michael Nazzareno Trimarchi Signed-off-by: Nishanth Menon Tested-by: Fabio Estevam

Merge git://git.denx.de/u-boot-imx

2018-06-27T17:09:55Z

common: Fix cpu nr type which is always unsigned type

2018-06-19T11:31:45Z

cpu_cmd() is reading cpu number via simple_strtoul() which is always unsigned type. Platform code implementations are not expecting that nr can be negative and there is not checking in the code for that too. This patch is using u32 type for cpu number to make sure that platform code get proper value range. Signed-off-by: Michal Simek

ARM: mxs: let boards override entire dram parameter table

2018-06-18T14:24:57Z

If many values differ from the defaults, overriding the full table is simpler and more space efficient than tweaking it through mxs_adjust_memory_params(). Signed-off-by: Mans Rullgard

Merge tag 'xilinx-for-v2018.07-rc2' of git://git.denx.de/u-boot-microblaze

2018-06-15T13:38:06Z

Xilinx fixes for v2018.07-rc2 Zynq: - Fix missing watchdog header - DT fixes ZynqMP: - emmc configuration split - Enable SPD - Fix PMUFW_INIT_FILE logic - Coverity fixes in SoC code timer - Add timer_get_boot_us mmc: - Fix MMC HS200 tuning command serial: - Fix scrabled chars with OF_LIVE

arm64: zynqmp: Check return value in zynqmp_mmio_rawwrite()

2018-06-15T06:54:05Z

There should be return value check from zynqmp_mmio_read() in zynqmp_mmio_rawwrite() to make sure that errors are propagated properly. Signed-off-by: Michal Simek