u-boot.git/arch/arm/cpu, branch v2019.04

armv8: Disable exception vectors in SPL by default

2019-03-22T16:15:03Z

Commit 1416e2d2253 ("armv8: make SPL exception vectors optional") had a typo in it which effectively disabled exception handling in SPL code always. Since nobody complained, I guess we may as well disable exception handling in SPL always by default. So fix the bug to make the config option effective, but disable exception handling in SPL by default. This gets us to the same functionality as before by default, but with much less code included in the binary. Signed-off-by: Alexander Graf Reviewed-by: Matthias Brugger Reviewed-by: Andre Przywara

armv7: ls102xa: Add workaround for DDR erratum A-008850

2019-03-15T06:22:01Z

Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu Signed-off-by: Alison Wang Reviewed-by: Prabhakar Kushwaha

armv8: fsl-layerscape: fix SEC QI ICID setup

2019-03-03T16:31:09Z

The SEC QI ICID setup in the QIIC_LS register is actually an offset that is being added to the ICID coming from the qman portal. Setting it with a non-zero value breaks SMMU setup as the resulting ICID is not known. On top of that, the SEC QI ICID must match the qman portal ICIDs in order to share the isolation context. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geanta Reviewed-by: Bharat Bhushan Reviewed-by: Prabhakar Kushwaha

armv8: ls1043a: move SCSI_AHCI and SCSI to arm/Kconfig

2019-02-19T04:56:44Z

remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface support. this changed is to fixed the ls1043ardb compile warning as fallows: ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal.See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Peng Ma [PK: reword the patch subject] Reviewed-by: Prabhakar Kushwaha

armv8: layerscape: move CONFIG_LAYERSCAPE to Kconfig

2019-02-19T04:56:44Z

Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms. Signed-off-by: Rajesh Bhagat Reviewed-by: Prabhakar Kushwaha

armv8: layerscape: move TZASC and TZPC configs to Kconfig

2019-02-19T04:56:44Z

Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig for LS1088A and LS2088A platforms. Signed-off-by: Rajesh Bhagat Reviewed-by: Prabhakar Kushwaha

lx2160aqds : Add support for LX2160AQDS platform

2019-02-19T04:56:44Z

LX2160AQDS is a development board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan Signed-off-by: Sriram Dash Signed-off-by: Pankaj Bansal Signed-off-by: Udit Agarwal [PK: Sqaush patch for "secure boot defconfig" & add maintainer] Signed-off-by: Prabhakar Kushwaha

armv8: emc2305: add support for fan controller

2019-02-19T04:56:43Z

Add support for fan controller emc2305. Signed-off-by: Sriram Dash Signed-off-by: Meenakshi Aggarwal Signed-off-by: Prabhakar Kushwaha

armv8: lx2160ardb : Add support for LX2160ARDB platform

2019-02-19T04:56:43Z

LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan Signed-off-by: Yogesh Gaur Signed-off-by: Meenakshi Aggarwal Signed-off-by: Vabhav Sharma Signed-off-by: Sriram Dash Signed-off-by: Rajesh Bhagat Signed-off-by: Pankit Garg Signed-off-by: Yinbo Zhu Signed-off-by: Peng Ma Signed-off-by: Chuanhua Han Signed-off-by: Priyanka Jain [PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han and re-arrange defconfig] Signed-off-by: Prabhakar Kushwaha

armv8: fsl-layerscape: reorder rgmii dpmacs' enablement

2019-02-19T04:56:43Z

some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal Reviewed-by: Prabhakar Kushwaha