<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/cpu, branch v2020.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu?h=v2020.10</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu?h=v2020.10'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2020-09-24T15:27:32Z</updated>
<entry>
<title>armv8: lx2160a: fix reset sequence</title>
<updated>2020-09-24T15:27:32Z</updated>
<author>
<name>Meenakshi Aggarwal</name>
<email>meenakshi.aggarwal@nxp.com</email>
</author>
<published>2020-09-09T08:36:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d31f3a1b62889d0bc1bbd801760e0b0a55bc02f6'/>
<id>urn:sha1:d31f3a1b62889d0bc1bbd801760e0b0a55bc02f6</id>
<content type='text'>
Make sure that SW_RST_REQ and RST_REQ_MSK are cleared
before triggering hardware reset request.

Signed-off-by: Thirupathaiah Annapureddy &lt;thiruan@linux.microsoft.com&gt;
Signed-off-by: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm64: Layerscape: Survive LPI one-way reset workaround</title>
<updated>2020-09-24T15:27:32Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2020-08-06T06:38:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=af288cb291da3abef6be0875527729296f7de7a0'/>
<id>urn:sha1:af288cb291da3abef6be0875527729296f7de7a0</id>
<content type='text'>
The workaround of LPI one-way reset issue is broken by the series:
https://patchwork.ozlabs.org/project/uboot/list/?series=192398

This patch is to add DT node for GIC RD tables and create corresponding
reserved-memory node in kernel DT to fix it.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>fsl-layerscape: enable dwc3 snooping feature</title>
<updated>2020-09-24T15:27:32Z</updated>
<author>
<name>Ran Wang</name>
<email>ran.wang_1@nxp.com</email>
</author>
<published>2020-08-05T07:07:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=223c19076f8b6808ffcb3772dd91d890d180cd65'/>
<id>urn:sha1:223c19076f8b6808ffcb3772dd91d890d180cd65</id>
<content type='text'>
Configure DWC3’s cache type to ‘cacheable’ for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.

Signed-off-by: Ran Wang &lt;ran.wang_1@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: Introduce xenguest_arm64 board</title>
<updated>2020-08-14T19:18:27Z</updated>
<author>
<name>Andrii Anisov</name>
<email>andrii_anisov@epam.com</email>
</author>
<published>2020-08-06T09:42:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=770a8eef3e27a5dc16e286cafa1a58e9201c9721'/>
<id>urn:sha1:770a8eef3e27a5dc16e286cafa1a58e9201c9721</id>
<content type='text'>
Introduce a minimal Xen guest board running as a virtual
machine under Xen Project's hypervisor [1], [2].

Part of the code is ported from Xen mini-os and also uses
work initially done by different authors from NXP: please see
relevant files for their copyrights.

[1] https://xenbits.xen.org
[2] https://wiki.xenproject.org/

Signed-off-by: Andrii Anisov &lt;andrii_anisov@epam.com&gt;
Signed-off-by: Oleksandr Andrushchenko &lt;oleksandr_andrushchenko@epam.com&gt;
Signed-off-by: Anastasiia Lukianenko &lt;anastasiia_lukianenko@epam.com&gt;
</content>
</entry>
<entry>
<title>ARM: add Kconfig option for PSCI 0.1</title>
<updated>2020-08-05T12:18:34Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.io</email>
</author>
<published>2020-07-31T18:56:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7f772fbcc04b8f70a70b79f869b03c2897ba0651'/>
<id>urn:sha1:7f772fbcc04b8f70a70b79f869b03c2897ba0651</id>
<content type='text'>
We still have some platforms that only implements functionalities in
PSCI 0.1 (e.g. Allwinner ARMv7 SoCs).

Add a Kconfig option for exporting only PSCI 0.1. The code to export
PSCI 0.1 is still available and gets activated by this patch.

In addition, default ARCH_SUNXI U-Boot PSCI implementation to export
PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core
ARMv7 SoCs.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
</content>
</entry>
<entry>
<title>arch: arm: use dt and UCLASS_SYSCON to get gic lpi details</title>
<updated>2020-07-29T14:37:11Z</updated>
<author>
<name>Rayagonda Kokatanur</name>
<email>rayagonda.kokatanur@broadcom.com</email>
</author>
<published>2020-07-26T17:07:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2ae7adc659f7fca9ea65df4318e5bca2b8274310'/>
<id>urn:sha1:2ae7adc659f7fca9ea65df4318e5bca2b8274310</id>
<content type='text'>
Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.

Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.

Signed-off-by: Rayagonda Kokatanur &lt;rayagonda.kokatanur@broadcom.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>board: ns3: add api to save boot parameters passed from BL31</title>
<updated>2020-07-29T14:13:41Z</updated>
<author>
<name>Abhishek Shah</name>
<email>abhishek.shah@broadcom.com</email>
</author>
<published>2020-07-15T17:18:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ef7192e4043d7724f0d063072092e00150fb1f5e'/>
<id>urn:sha1:ef7192e4043d7724f0d063072092e00150fb1f5e</id>
<content type='text'>
Add API to save boot parameters passed from BL31

Use assembly implementation of save_boot_params instead of c function.
Because generally ATF does not set up SP_EL2 on exiting.
Thus, usage of a C function immediately after exiting with no stack
setup done by ATF explicitly, may cause SP_EL2 to be not sane,
which in turn causes a crash if this boot was not lucky to get
an SP_EL2 in valid range. Replace C implementation with assembly one
which does not use stack this early, and let u-boot to set up its stack
later.

Signed-off-by: Abhishek Shah &lt;abhishek.shah@broadcom.com&gt;
Signed-off-by: Rajesh Ravi &lt;rajesh.ravi@broadcom.com&gt;
Signed-off-by: Vladimir Olovyannikov &lt;vladimir.olovyannikov@broadcom.com&gt;
Signed-off-by: Rayagonda Kokatanur &lt;rayagonda.kokatanur@broadcom.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: cpu: armv8: add L3 memory flush support</title>
<updated>2020-07-29T14:13:40Z</updated>
<author>
<name>Rayagonda Kokatanur</name>
<email>rayagonda.kokatanur@broadcom.com</email>
</author>
<published>2020-07-15T17:18:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5d9302d478813f6bdd79393eedde76dcf512f403'/>
<id>urn:sha1:5d9302d478813f6bdd79393eedde76dcf512f403</id>
<content type='text'>
Add L3 memory flush support for NS3.

Signed-off-by: Rayagonda Kokatanur &lt;rayagonda.kokatanur@broadcom.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: add support for SoC s5p4418 (cpu) / nanopi2 board</title>
<updated>2020-07-29T12:43:40Z</updated>
<author>
<name>Stefan Bosch</name>
<email>stefan_b@posteo.net</email>
</author>
<published>2020-07-10T17:07:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d1611086e0058c0b701cd487fc9735ffcc9c6c4c'/>
<id>urn:sha1:d1611086e0058c0b701cd487fc9735ffcc9c6c4c</id>
<content type='text'>
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- SPL not supported yet --&gt; no spl-dir in arch/arm/cpu/armv7/s5p4418/.
  Appropriate line in Makefile removed.
- cpu.c: '#include &lt;cpu_func.h&gt;' added.
- arch/arm/cpu/armv7/s5p4418/u-boot.lds removed, is not required
  anylonger.
- "obj-$(CONFIG_ARCH_NEXELL) += s5p-common/" added to
  arch/arm/cpu/armv7/Makefile since s5p-common/pwm.c is used instead
  of drivers/pwm/pwm-nexell.c.
- s5p4418.dtsi: '#include "../../../include/generated/autoconf.h"'
  removed, is not necessary, error at out-of-tree building.
  '#ifdef CONFIG_CPU_NXP4330'-blocks (2x) removed. Some minor changes
  regarding mmc. 'u-boot,dm-pre-reloc' added to dp0 because of added
  DM_VIDEO support.
- board/s5p4418/ renamed to board/friendlyarm/
- All s5p4418-boards except nanopi2 removed because there is no
  possibility to test the other boards.
- Kconfig: Changes to have a structure like mach-bcm283x (RaspberryPi),
  e.g. "config ..." entries moved from/to other Kconfig.
- "CONFIG_" removed from several s5p4418/nanopi2 specific defines
  because the appropriate values do not need to be configurable.
- nanopi2/board.c: All getenv(), getenv_ulong(), setenv() and saveenv()
  renamed to env_get(), env_get_ulong(), env_set() and env_save(),
  respectively. MACH_TYPE_S5P4418 is not defined anymore, therefore
  appropriate code removed (not necessary for DT-kernels).
- nanopi2/onewire.c: All crc8() renamed to crc8_ow() because crc8() is
  already defined in lib/crc8.c (with different parameters).
- dts: "nexell,s5pxx18-i2c" used instead of "i2c-gpio", i2c0 and
  i2c1 added. gmac-, ehci- and dwc2otg-entries removed because the
  appropriate functionality is not supported yet. New mmc-property
  "mmcboost" added.
  s5p4418-pinctrl.dtsi: gmac-entries removed, mmc- and i2c-entries
  added.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
  possible (and similar).

Signed-off-by: Stefan Bosch &lt;stefan_b@posteo.net&gt;
</content>
</entry>
<entry>
<title>pwm: add driver for nexell</title>
<updated>2020-07-29T12:43:40Z</updated>
<author>
<name>Stefan Bosch</name>
<email>stefan_b@posteo.net</email>
</author>
<published>2020-07-10T17:07:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=18284c1d56bfe2b51484561881377489ffa86c3b'/>
<id>urn:sha1:18284c1d56bfe2b51484561881377489ffa86c3b</id>
<content type='text'>
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- Since drivers/pwm/pwm-nexell.c is an adapted version of
  s5p-common/pwm.c an appropriately changed version of s5p-common/pwm.c
  is used instead. Therefore arch/arm/mach-s5pc1xx/include/mach/pwm.h
  copied to arch/arm/mach-nexell/include/mach and s5p-common/Makefile
  changed appropriately.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
  possible (and similar).

Signed-off-by: Stefan Bosch &lt;stefan_b@posteo.net&gt;
</content>
</entry>
</feed>
