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<title>u-boot.git/arch/arm/cpu, branch v2021.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu?h=v2021.01</id>
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<updated>2020-12-10T08:26:39Z</updated>
<entry>
<title>arm: ls102xa: select USB PHY erratum's only if USB is enabled</title>
<updated>2020-12-10T08:26:39Z</updated>
<author>
<name>Aleksandar Gerasimovski</name>
<email>aleksandar.gerasimovski@hitachi-powergrids.com</email>
</author>
<published>2020-11-26T10:52:41Z</published>
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<id>urn:sha1:2ef53647d10ac0ec6938b37e5d9cc457ff585cdf</id>
<content type='text'>
The USB support is not by default enabled on all designs, so it does not
make seance to have USB specific erratum's enabled on such a designs.

On our internal Hitachi-Powergrids design not using the USB controller
there is a crash when accessing those specific memory locations selected
by the erratum flags.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A</title>
<updated>2020-12-10T08:26:39Z</updated>
<author>
<name>Alban Bedel</name>
<email>alban.bedel@aerq.com</email>
</author>
<published>2020-11-17T15:20:04Z</published>
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<id>urn:sha1:cbf77d201870f2d12227e2d95718a416b16ec98b</id>
<content type='text'>
When booting from TF-A there is a logic that attempt to detect if the
default environment is used, if this is the case it then set the
`bootcmd` and `mcinitcmd` depending of the device we booted from.
This detection logic is dubious as it access internals of the env
implementation and it doesn't always work correctly.

First of all it detect any valid environment as not being the
default, so after running `env default -a &amp;&amp; saveenv` the board
doesn't boot anymore as `bootcmd` is then empty.
But it also fails in some other ways, for example it always detect a
default environment when redundant env is enabled on MMC, so in that
case `bootcmd` is overwritten on every boot.

Instead of increasing the complexity of the detection just check if
`bootcmd` and `mcinitcmd` are set in the environment and set them if
they are not.

Signed-off-by: Alban Bedel &lt;alban.bedel@aerq.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>layerscape: fdt.c: Check for NULL return value from fdt_getprop()</title>
<updated>2020-12-10T08:26:39Z</updated>
<author>
<name>Priyanka Singh</name>
<email>priyanka.singh@nxp.com</email>
</author>
<published>2020-11-02T06:08:41Z</published>
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<id>urn:sha1:03d095e87d4b6865deae74527c9655161a891777</id>
<content type='text'>
Check for NULL return value from fdt_getprop() in
fdt_fixup_remove_jr()

Signed-off-by: Priyanka Singh &lt;priyanka.singh@nxp.com&gt;
[Fixed checkpatch errors/warnings]
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: lx2162a: Add Soc changes to support LX2162A</title>
<updated>2020-12-10T08:26:39Z</updated>
<author>
<name>Meenakshi Aggarwal</name>
<email>meenakshi.aggarwal@nxp.com</email>
</author>
<published>2020-10-29T13:46:16Z</published>
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<id>urn:sha1:3a187cff7ac95887917bcf25f3f575bb677a361e</id>
<content type='text'>
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.

LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.

Signed-off-by: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: layerscape: don't remove crypto node if just partially disabled</title>
<updated>2020-10-23T11:22:09Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2020-10-16T17:38:18Z</published>
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<id>urn:sha1:4eecc6f1a104b5f3737c7e1bbaaa022e5d3bac53</id>
<content type='text'>
On all newer Layerscape SoCs, only the export-controlled ciphers of the
crypto module are disabled on non-E parts. Thus it doesn't make sense to
completely remove the node. Linux will figure out what is there and what
is not.

Just remove it for older SoCs, where the module is indeed completely
disabled on non-E parts.

Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Reviewed-by: Horia Geanta &lt;horia.geanta@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>net: lx2160a.c: Update to set ECx_PMUX precedence</title>
<updated>2020-10-23T11:22:09Z</updated>
<author>
<name>Razvan Ionut Cirjan</name>
<email>razvanionut.cirjan@nxp.com</email>
</author>
<published>2020-10-23T10:50:38Z</published>
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<id>urn:sha1:c760095adbf222aefba00404b38a25bf5dee0909</id>
<content type='text'>
As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.

Signed-off-by: Razvan Ionut Cirjan &lt;razvanionut.cirjan@nxp.com&gt;
[Rebased]
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: layerscape: add a way of specifying additional iommu mappings</title>
<updated>2020-10-23T11:22:09Z</updated>
<author>
<name>Laurentiu Tudor</name>
<email>laurentiu.tudor@nxp.com</email>
</author>
<published>2020-09-10T09:42:19Z</published>
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<id>urn:sha1:2a5bbb13cc39102a68fcc31056925427ab44b591</id>
<content type='text'>
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more static scenarios such as hardwired PCI endpoints
that get initialized later in the system setup) that would allow
two things:
 - for a SRIOV capable PCI EP identified by its B.D.F specify
   the maximum number of VFs that will ever be created for it
 - for hot-plug case, specify the B.D.F with which the device
   will show up on the PCI bus
More details can be found in the included documentation:
  arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra

Signed-off-by: Laurentiu Tudor &lt;laurentiu.tudor@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm: fsl-layerscape: Include device_compat.h in soc.c</title>
<updated>2020-10-16T13:44:27Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-10-16T01:44:15Z</published>
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<id>urn:sha1:e1f306c07cc775721bccba3ae412521b12367002</id>
<content type='text'>
Necessary for dev_xxx.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm64: PIE: Skip fixups if distance is zero</title>
<updated>2020-10-08T15:42:36Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2020-09-30T16:39:14Z</published>
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<id>urn:sha1:9a984f100ed1d2d4a3aed7db9cfd1a3892e2bccd</id>
<content type='text'>
When the actual offset between link and runtime address is zero, there
is no need for patching up U-Boot early when running with
CONFIG_POSITION_INDEPENDENT.

Skip the whole routine when the distance is 0.

This helps when U-Boot is loaded into ROM, or in otherwise sensitive
memory locations.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'next'</title>
<updated>2020-10-05T18:10:59Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-10-05T17:05:46Z</published>
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<id>urn:sha1:b7e7831e5d5be047f421ddc1f308afc22764a893</id>
<content type='text'>
Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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