u-boot.git/arch/arm/cpu, branch v2024.01

Revert "arm64: Use FEAT_HAFDBS to track dirty pages when available"

2023-11-17T16:58:26Z

This reverts commit 6cdf6b7a340db4ddd008516181de7e08e3f8c213. This is part of a series trying to make use of the arm64 hardware features for tracking dirty pages. Unfortunately this series causes problems for the AC5/AC5X SoCs. Having exhausted other options the consensus seems to be reverting this series is the best course of action. Signed-off-by: Chris Packham

Revert "arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is present"

2023-11-17T16:58:26Z

This reverts commit 836b8d4b205d2175b57cb9ef271e638b0c116e89. This is part of a series trying to make use of the arm64 hardware features for tracking dirty pages. Unfortunately this series causes problems for the AC5/AC5X SoCs. Having exhausted other options the consensus seems to be reverting this series is the best course of action. Signed-off-by: Chris Packham

Revert "armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present"

2023-11-17T16:58:26Z

This reverts commit c1da6fdb5c239b432440721772d993e63cfdeb20. This is part of a series trying to make use of the arm64 hardware features for tracking dirty pages. Unfortunately this series causes problems for the AC5/AC5X SoCs. Having exhausted other options the consensus seems to be reverting this series is the best course of action. Signed-off-by: Chris Packham

tree-wide: Replace http:// link with https:// link for ti.com

2023-11-10T16:01:50Z

Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon

sunxi: psci: implement PSCI on R528

2023-10-22T22:41:52Z

This patch adds the necessary code to make nonsec booting and PSCI secondary core management functional on the R528/T113. Signed-off-by: Sam Edwards Tested-by: Maksim Kiselev Tested-by: Kevin Amadiva Reviewed-by: Andre Przywara

sunxi: psci: stop modeling register layout with C structs

2023-10-22T22:41:52Z

Since the sunxi support nowadays generally prefers #defined register offsets instead of modeling register layouts using C structs, now is a good time to do this for PSCI as well. This patch moves away from using the structs `sunxi_cpucfg_reg` and `sunxi_prcm_reg` in psci.c. The former struct and its associated header file existed only to support PSCI code, so also delete them altogether. Signed-off-by: Sam Edwards Reviewed-by: Andre Przywara

sunxi: psci: refactor register access to separate functions

2023-10-22T22:41:52Z

This is to prepare for R528, which does not have the typical "CPUCFG" block; it has a "CPUX" block which provides these same functions but is organized differently. Moving the hardware-access bits to their own functions separates the logic from the hardware so we can reuse the same logic. Signed-off-by: Sam Edwards Reviewed-by: Andre Przywara

sunxi: psci: clean away preprocessor macros

2023-10-22T22:41:52Z

This patch restructures psci.c to get away from the "many different function definitions switched by #ifdef" paradigm to the preferred style of having a single function definition with `if (IS_ENABLED(...))` to make the optimizer include only the appropriate function bodies instead. There are no functional changes here. Signed-off-by: Sam Edwards Reviewed-by: Andre Przywara

sunxi: refactor serial base addresses to avoid asm/arch/cpu.h

2023-10-22T22:41:52Z

At the moment we have each SoC's memory map defined in its own cpu.h, which is included in include/configs/sunxi_common.h. This will be a problem with the introduction of Allwinner RISC-V support. Remove the inclusion of that header file from the common config header, instead move the required serial base addresses (for the SPL) into a separate header file. Then include the original cpu.h file only where we really need it, which is only under arch/arm now. This disentangles the architecture specific header files from the generic code. Signed-off-by: Andre Przywara

ARM: psci: move GIC address override to Kconfig

2023-10-11T17:22:32Z

As the code to switch an ARM core from secure to the non-secure state needs to know the base address of the Generic Interrupt Controller (GIC), we read an Arm Cortex defined system register that is supposed to hold that base address. However there are SoCs out there that get this wrong, and this CBAR register either reads as 0 or points to the wrong address. To accommodate those systems, so far we use a macro defined in some platform specific header files, for affected boards. To simplify future extensions, replace that macro with a Kconfig variable that holds this override address, and define a default value for SoCs that need it. Signed-off-by: Andre Przywara Reviewed-by: Sam Edwards