u-boot.git/arch/arm/cpu, branch v2026.04

arm: armv8: Flush TLB before enabling MMU

2026-02-24T14:16:06Z

Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable") broke Apple Silicon machines in certain scenarios. If the MMU is currently not enabled we need to flush the TLB before we enable it to prevent stale TLB entries from becoming active again. So move the __asm_invalidate_tlb_all() back immediately before the mmu_setup() call. Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable") Signed-off-by: Mark Kettenis Reviewed-by: Ilias Apalodimas

arm: spl: Ensure 8 byte alignment of appended DTB without separate BSS

2026-02-09T15:33:20Z

Historically, when we have an appended device tree and also our resulting binary will contain the BSS section, we have ensured that everything will be where it's expected to be by declaring that the BSS is overlayed with a symbol matches the end of the port of the ELF binary that is objcopy'd to the binary we concatenate with. This in turn means that the logic to generate a "pad" file, which is the size found in the __bss_size symbol, will be correct and then we can concatenate the device tree and it will begin at __bss_size at run time. With commit 5ffc1dcc26d3 ("arm: Remove rel.dyn from SPL linker scripts") we removed this overlay as part of trying to ensure that we met both the requirements of the device tree to be 8 byte aligned as well as that our logic to generate the -pad file would match what ended up in the resulting binary. While it was correct to remove an unused section it did not solve ultimately solve the problem for all cases. To really fix the problem, we need to do two things. First, our final section prior to _image_binary_end must be 8 byte aligned (for the case of having a separate BSS and so our appended DTB exists at this location). This cannot be '.binman_sym_table' as it may be empty, and in turn the ELF type would be NOBITS and so not copied with objcopy. The __u_boot_list section will never be empty, so it is our final section, and ends with a '. = ALIGN(8)' statement. Second, as this is the end of our copied data it is safe to declare that the BSS starts here, so use the OVERLAY keyword to place the BSS here. Fixes: 5ffc1dcc26d3 ("arm: Remove rel.dyn from SPL linker scripts") Reported-by: Brian Sune Reported-by: Phil Phil Sutter Tested-by: Brian Sune Tested-by: Phil Sutter Tested-by: Greg Malysa Signed-off-by: Tom Rini

armv8: u-boot-spl.lds: Place binman symbols at end of binary

2026-01-28T20:41:21Z

It can be useful in xPL to access symbols from binman, such as the offset/position and size of a binman entry. Place these binman symbols together at the end of the xPL binary for ARMv8, similar to ARM and RISC-V. Signed-off-by: Jonas Karlman Reviewed-by: Simon Glass

arm: Remove rel.dyn from SPL linker scripts

2026-01-28T18:57:01Z

As of v2026.01, no platforms contain any rel.dyn sections in their xPL phase images. Their inclusion in linker scripts initially was an oversight as part of taking the full U-Boot linker scripts and modifying them down. Then in commit 8b0ebe054bb3 ("arm: Update linker scripts to ensure appended device tree is aligned") these sections were used to force correct alignment for the device tree. This however, lead to a different problem. That problem is that when we do not have a separate BSS section in SPL we instead would overlay the BSS with the rel.dyn section, in the common linker script case. This in turn lead to creating an incorrectly sized BSS "pad" file sometimes (depending on arbitrary changes within the rest of the binary itself). This in turn lead to the dtb being in the wrong location in the binary and not found at run time. This commit fixes a few things: - Remove the rel.dyn section from all ARM SPL linker scripts. - In turn, this moves the dtb alignment statement in to another section. - For ast2600 which uses CONFIG_POSITION_INDEPENDENT we need to keep the symbols however. Tested-by: Fabio Estevam Reported-by: Fabio Estevam Co-developed-by: Ilias Apalodimas Reviewed-by: Chia-Wei, Wang Signed-off-by: Tom Rini

board: nxp: Rename board directory from board/freescale to board/nxp

2026-01-28T06:26:50Z

This patch renames the board directory from board/freescale to board/nxp because NXP now provides Board Support Packages (BSPs) and tools for the former Freescale i.MX and other i.MX products. All relevant references have been updated accordingly. This change does not affect functionality. Signed-off-by: Alice Guo Reviewed-by: Fabio Estevam

Revert "arm: spl: Correct alignment of .rel.dyn section"

2026-01-26T17:00:02Z

This reverts commit 380ddb473c6bdf87e66c0fb93e256d1e233c6f5b. Signed-off-by: Tom Rini

arm: spl: Correct alignment of .rel.dyn section

2026-01-26T16:46:23Z

With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c") we now require the correct, 8 byte alignment of a device tree in order to work with it ourselves. This has exposed a number of issues. In the case of using arch/arm/cpu/u-boot-spl.lds for an xPL phase and having the BSS be overlayed with the dynamic relocations sections (here, .rel.dyn) we had missed adding the comment about our asm memset requirements. Then, when adjusting ALIGN statements we later missed this one. In turn, when we use objcopy to create our binary image we end up in the situation where where the BSS must start out 8 byte aligned as well as end 8 byte aligned because for appended device tree the requirement is that the whole BSS (which we add as padding to the binary) must be 8 byte aligned. Otherwise we end up with the situation where __bss_end (where we look for the device tree at run time) is aligned but the size of the BSS we add Fixes: 7828a1eeb2a1 ("arm: remove redundant section alignments") Fixes: 52caad0d14a3 ("ARM: Align image end to 8 bytes to fit DT alignment") Reported-by: Fabio Estevam Tested-by: Fabio Estevam Signed-off-by: Tom Rini --- Cc: Ilias Apalodimas Cc: Marek Vasut

arm: Update linker scripts to ensure appended device tree is aligned

2026-01-20T18:06:41Z

With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our device tree is not 8-byte aligned. In commit 85f586035d75 ("ARM: OMAP2+: Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains that we must have ALIGN(x) statements inside of a section to ensure that padding is included and not simply that the linker address counter is incremented. To that end, this patch: - Expands some linker sections to be more readable when adding a second statement to the section. - Aligns the final section before _end (for U-Boot) or _image_binary_end or __bss_end (for xPL phases) by 8-bytes by adding '. = ALIGN(8);' to the final section before the symbol. - Ensure that we do have alignment by adding an ASSERT so that when not aligned we fail to link (and explain why). - Remove now-spurious '. = ALIGN(x);' statements that were intended to provide the above alignments. Tested-by: Michal Simek # Zynq Reviewed-by: Ilias Apalodimas [trini: Also update arch/arm/cpu/armv8/u-boot.lds as Ilas requested] Signed-off-by: Tom Rini

kbuild: Bump the build system to 6.1

2026-01-02T16:28:14Z

Our last sync with the kernel was 5.1. We are so out of sync now, that tracking the patches and backporting them one by one makes little sense and it's going to take ages. This is an attempt to sync up Makefiles to 6.1. Unfortunately due to sheer amount of patches this is not easy to review, but that's what we decided during a community call for the bump to 5.1, so we are following the same guidelines here. Signed-off-by: Sughosh Ganu Signed-off-by: Ilias Apalodimas a #rebased on -next

armv8/fsl-layerscape: fdt: Remove offline cores from cooling device maps

2025-12-11T11:16:32Z

Some processor families use a generic device tree, and rely on u-boot fixups to massage that for lower core count personalities (i.e. NXP LX2* family). For example, the LX2160A device tree will be used and then modified to offline non-existent cores when running on an 8-core LX2080A. However, the cooling maps still contain references to the non-existent core phandles, resulting in: OF: /thermal-zones/cluster6-7-thermal/cooling-maps/map0: could not find phandle 15 Rebuild the cooling maps as non-existent cores are deleted. Signed-off-by: Anthony Pighin Signed-off-by: Peng Fan