u-boot.git/arch/arm/dts/Makefile, branch main

arm: mvebu: Add Allied Telesis x960 board

2026-07-30T20:06:23Z

The x960-28YSQ is a 25G/100G layer 3 switch from Allied Telesis. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese [sr: fix DT file name in MAINTAINERS]

arm: dts: Add SD dts for the sc598 EZKIT

2026-07-28T18:30:55Z

The eMMC and SD card on the sc598 share pins, so they cannot be used at the same time. Previously, this was managed with a patch applied by the relevant build system, but patches are brittle and have to be maintained. Instead, they have been replaced with two separate device trees , one for eMMC and one for SD card, which inherit a shared base dtsi. The build system can then select between the default device tree which enabled eMMC or the other device tree which enables SD card support. Signed-off-by: Caleb Ethridge

Merge patch series "arm: aspeed: add initial AST2700 SoC support"

2026-06-29T21:29:56Z

Ryan Chen says: AST2700 is the 8th generation of Integrated Remote Management Processor introduced by ASPEED Technology Inc. It is a Board Management Controller (BMC) SoC family with a dual-die architecture: SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs, clock dividers and reset domains. Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com

arm: dts: aspeed: Add initial AST27xx SoC device tree

2026-06-29T19:43:20Z

Add initial device tree support for the ASPEED AST27xx family, the 8th-generation Baseboard Management Controller (BMC) SoCs. AST27xx SOC Family - https://www.aspeedtech.com/server_ast2700/ - https://www.aspeedtech.com/server_ast2720/ - https://www.aspeedtech.com/server_ast2750/ The AST27xx features a dual-SoC architecture consisting of two ties, referred to as SoC0 and SoC1 - interconnected through an internal property bus. Both SoCs share the same address decoding scheme, while each maintains independent clock and reset domains. - SoC0 (CPU die): contains a dual-core Cortex-A35 cluster and two Cortex-M4 cores, along with high-speed peripherals. - SoC1 (I/O die): includes the BootMCU (responsible for system boot) and its own clock/reset domains low-speed peripherals. The device tree describes the SoC0 and SoC1 domains and their peripheral layouts. Signed-off-by: Ryan Chen

Merge tag 'v2026.07-rc5' into next

2026-06-22T22:42:41Z

Prepare v2026.07-rc5

arm: dts: Move remaining am335x-bone* to OF_UPSTREAM

2026-06-12T19:01:24Z

These boards are not yet in the CONFIG_OF_LIST of the defconfigs, add them and remove the local devicetrees. Signed-off-by: Markus Schneider-Pargmann (TI)

arm: dts: am335x: Remove unused uboot devicetrees

2026-06-12T19:01:24Z

These devicetrees are not used anymore because the boards are using upstream devicetrees now. Acked-by: Andrew Davis Signed-off-by: Markus Schneider-Pargmann (TI)

Merge patch series "This series introduces initial U-Boot support for mach-axiado AX3005 SCM3005 board, a quad-core ARM Cortex-A53 (ARMv8/ARM64) platform."

2026-06-11T13:51:13Z

Siu Ming Tong says: Patch 1 adds the device tree files: an SoC-level DTSI describing GIC-v3, Cadence/Zynq UART, a fixed reference clock, and spin-table secondary CPU boot, plus a board-level DTS setting the console to uart3 at 115200 baud with 2 GB DRAM at 0x80000000. Patch 2 adds mach-axiado to support Axiado SoC-based boards, Kconfig plumbing (AXIADO_AX3005 and TARGET_SCM3005), defconfig, board source with ft_board_setup() and a MAINTAINERS entry. Tested on SCM3005 EVK hardware Link: https://lore.kernel.org/r/20260527-review-v2-0-10daefddf47d@axiado.com

arm64: dts: axiado: Add AX3005 SCM3005 device tree

2026-06-10T20:52:25Z

Add device tree source files for the Axiado AX3005 SCM3005 board. The AX3005 is a quad-core 64-bit ARMv8 Cortex-A53 SoC. The DTSI describes the SoC-level nodes: GIC-v3 interrupt controller, Cadence/Zynq UART, fixed reference clock, and spin-table secondary CPU boot. A /memreserve/ directive protects the spin-table release address at 0x80002fa0 from being overwritten during boot. The SCM3005 DTS sets the console to uart3 at 115200 baud and declares 2 GB of DRAM starting at 0x80000000. Tested-by: Siu Ming Tong Signed-off-by: Karthikeyan Mitran Signed-off-by: Siu Ming Tong

board: freebox: add Nodebox 10G board support

2026-06-10T09:23:26Z

Add board support for the Freebox Nodebox 10G based on the Marvell Armada 8040 SoC. This board features: - Quad-core ARMv8 AP806 with dual CP110 companions - eMMC storage via Xenon SDHCI controller - 1G SGMII Ethernet on CP0 lane 5 - I2C buses for peripheral access - NS16550 UART console at 115200 baud The implementation includes: - Device tree for the Nodebox 10G hardware - Dedicated board directory (board/freebox/nbx10g/) - Board-specific Kconfig and defconfig The U-Boot comphy bindings (phy-type/phy-speed) differ from the mainline Linux PHY framework bindings used by phy-mvebu-cp110-comphy, so U-Boot and the kernel each have their own device tree. Signed-off-by: Vincent Jardin Reviewed-by: Stefan Roese