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<title>u-boot.git/arch/arm/dts, branch master</title>
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<updated>2026-06-16T03:38:25Z</updated>
<entry>
<title>arm: dts: renesas: Enable DBSC5 on R-Car R8A78000 X5H Cortex-M33 RSIP port</title>
<updated>2026-06-16T03:38:25Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2026-06-10T18:20:59Z</published>
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<id>urn:sha1:28f675023da174b1b4817266cac7bcf3ffb6d908</id>
<content type='text'>
Bind the DBSC5 DRAM controller driver on boot in board_early_init_r(),
which brings up the DBSC5 DRAM controller and its PHY and which enables
access to DRAM present on this system.

Add default boot command which loads additional bootloader components
from HF and UFS storage into SRAM and DRAM, and starts those components
on SCP and AP core 0. The system is then capable of reaching U-Boot on
the AP core 0. Specifically, the following components are loaded:
- SCP firmware, 384 kiB from HF offset 0x4c0000 to SCP STCM
- TFA BL31, 256 kiB from UFS0 offset 0x5000 * 4 kiB sectors to DRAM 0x8c200000
- TEE, 2 MiB from UFS0 offset 0x5200 * 4 kiB sectors to DRAM 0x8c400000
- U-Boot, 1 MiB from UFS0 offset 0x7200 * 4 kiB sectors to DRAM 0x8c300000
- IPL parameters table is generated at DRAM address 0x8c100000

Enable pstore command support to allow dumping kernel console from
pstore/ramoops, which is convenient for debugging. Use as follows:
=&gt; pstore set 0x80000000 0x10000 0x400 0x8000 0 0 0
=&gt; pstore display console

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-rockchip-20260610' of https://source.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2026-06-10T19:12:35Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-06-10T19:12:13Z</published>
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<id>urn:sha1:3cdce049f90d77c3f9221f1eb73922384c8972c3</id>
<content type='text'>
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/30398

Please pull the updates for rockchip platform:
- New Board support: rk3588 FriendlyElec NanoPi R76S
- UFS boot from SPL for rk3576 (NanoPi M5, ROCK 4D)
- Clock support for RK3576 GMAC 25MHz output and RK3528/RK3576 USB3 OTG
- Switch rk3128/rk3229 boards to upstream devicetree
- MAINTAINERS update for upstream devicetree references
- rk3588-rock-5b: Remove USB-C controller from u-boot.dtsi
</content>
</entry>
<entry>
<title>Merge branch 'qcom-main' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon</title>
<updated>2026-06-10T19:11:35Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-06-10T19:11:35Z</published>
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<id>urn:sha1:a30fd0895d1c7cabedac6de79c46a32c9543bd8e</id>
<content type='text'>
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/30394

- Define memory map for lemans-evk (pending SMEM)
- Fix CONFIG_SYS_INIT_SP_BSS_OFFSET in db410c chainloaded fragment
- Fix the "dump bootargs" command in the qcom-phone boot menu
- Fix a bug in the rpmh-regulator driver where the regulator mode may
  not be set during enable.
- Enable watchdog autostart for Dragonwing boards
- Fix serial console init on ipq5424-rdp466
</content>
</entry>
<entry>
<title>arm: dts: ipq5424-rdp466: add chosen node for serial console</title>
<updated>2026-06-10T11:36:18Z</updated>
<author>
<name>Gurumoorthy Santhakumar</name>
<email>gurumoorthy.santhakumar@oss.qualcomm.com</email>
</author>
<published>2026-06-03T11:38:53Z</published>
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<id>urn:sha1:757a95c7faae4bdc10dc463c1bb3cf3fee1418a0</id>
<content type='text'>
Add a /chosen node with stdout-path pointing to serial0 (uart1) to
enable the DT-driven console discovery path in
serial_find_console_or_panic().

Without this node, the live DT path in serial_find_console_or_panic()
is skipped and the fallback path is used. Adding the /chosen node makes
the console selection explicit and deterministic, ensuring the correct
serial device is always selected as the console.

Signed-off-by: Gurumoorthy Santhakumar &lt;gurumoorthy.santhakumar@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260603113853.3396271-1-gurumoorthy.santhakumar@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>dts: lemans-evk-u-boot: add override dtsi</title>
<updated>2026-06-10T11:36:18Z</updated>
<author>
<name>Aswin Murugan</name>
<email>aswin.murugan@oss.qualcomm.com</email>
</author>
<published>2026-04-24T10:42:37Z</published>
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<id>urn:sha1:c2019e01d069c398921abdf8f159136f7e550078</id>
<content type='text'>
Add initial support for the lemans EVK platform based on lemans SoC.
Define memory layout statically.

Signed-off-by: Aswin Murugan &lt;aswin.murugan@oss.qualcomm.com&gt;
Signed-off-by: Sumit Garg &lt;sumit.garg@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260424104237.968195-1-sumit.garg@kernel.org
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge patch series "ti: j7: Update to v0.12.0 of DDR config tool"</title>
<updated>2026-06-09T16:26:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-06-09T16:26:36Z</published>
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<id>urn:sha1:cf81e36fa0c85117dbfc9a8b606671eb4b25b9db</id>
<content type='text'>
Neha Malcom Francis &lt;n-francis@ti.com&gt; says:

Update all DDR configuration DTSIs to the latest auto-generated output of
the Sysconfig Tool (DDR Configuration for TDA4x, DRA8x, AM67x, AM68x,
AM69x (0.12.00.0000)) [0]

The auto-generated files must not be modified, but effort will be taken to
change the tool output to adhere to the latest checkpatch.pl rules. J722S
and J721E will also be updated in a subsequent series.

All the changes have been kernel boot tested and memtester has passed (same
as v1, as no functional changes made).

[0] https://dev.ti.com/sysconfig/#/start

Link: https://lore.kernel.org/r/20251103071035.674604-1-n-francis@ti.com
</content>
</entry>
<entry>
<title>arm: dts: k3-j742s2: ddr: Update to v0.12.0 of DDR config tool</title>
<updated>2026-06-09T16:26:21Z</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-11-03T07:10:34Z</published>
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<id>urn:sha1:54fb646ca42444f0756a6f1f4ecff7d027a70a96</id>
<content type='text'>
Update the DDR configuration for J742S2 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool</title>
<updated>2026-06-09T16:26:21Z</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-11-03T07:10:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fe22382b6454d9e92b5f32343ba8eac2e0d838d8'/>
<id>urn:sha1:fe22382b6454d9e92b5f32343ba8eac2e0d838d8</id>
<content type='text'>
Update the DDR configuration for AM69 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: dts: k3-j784s4: ddr: Update to v0.12.0 of DDR config tool</title>
<updated>2026-06-09T16:26:21Z</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-11-03T07:10:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c70fd4e5a291147151da1162effe5e20f6aed413'/>
<id>urn:sha1:c70fd4e5a291147151da1162effe5e20f6aed413</id>
<content type='text'>
Update the DDR configuration for J784S4 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: dts: k3-am68: ddr: Update to v0.12.0 of DDR config tool</title>
<updated>2026-06-09T16:26:21Z</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-11-03T07:10:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=168681795981a07d0ff301ffb61d9a596127decf'/>
<id>urn:sha1:168681795981a07d0ff301ffb61d9a596127decf</id>
<content type='text'>
Update the DDR configuration for AM68 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
</content>
</entry>
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