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<updated>2026-07-03T16:10:34Z</updated>
<entry>
<title>Merge patch series "TI: AM64-EVM/SK: Enable MAIN UART1 for SYSFW tracing"</title>
<updated>2026-07-03T16:10:34Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-07-03T16:10:34Z</published>
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<id>urn:sha1:476bea8b0ce95da2741dcb0be2b107384ce7c806</id>
<content type='text'>
Vishal Mahaveer &lt;vishalm@ti.com&gt; says:

Collecting SYSFW traces from DMSC firmware is broken on the current
codebase. These changes enables MAIN_UART1 for collecting SYSFW traces
when the trace option is enabled in the boardcfg.

Link: https://lore.kernel.org/r/20260605193829.395161-1-vishalm@ti.com
</content>
</entry>
<entry>
<title>arm: dts: k3-am642-evm/sk: enable MAIN UART1 for SYSFW logs</title>
<updated>2026-07-03T16:09:56Z</updated>
<author>
<name>Vishal Mahaveer</name>
<email>vishalm@ti.com</email>
</author>
<published>2026-06-05T19:38:29Z</published>
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<id>urn:sha1:48b7c05d272747ec4d8f8f7eb53119ef149dcc7a</id>
<content type='text'>
Enable MAIN UART1 in the R5 SPL device tree to collect system SYSFW
debug traces during early boot.

Signed-off-by: Vishal Mahaveer &lt;vishalm@ti.com&gt;
Reviewed-by: Bryan Brattlof &lt;bb@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "arm: aspeed: add initial AST2700 SoC support"</title>
<updated>2026-06-29T21:29:56Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-06-29T19:44:52Z</published>
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<id>urn:sha1:0d8e33717d7e5b2a4034cc88f18bf233f77801e7</id>
<content type='text'>
Ryan Chen &lt;ryan_chen@aspeedtech.com&gt; says:

AST2700 is the 8th generation of Integrated Remote Management
Processor introduced by ASPEED Technology Inc. It is a Board
Management Controller (BMC) SoC family with a dual-die architecture:
SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and
SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs,
clock dividers and reset domains.

Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com
</content>
</entry>
<entry>
<title>arm: dts: aspeed: Add initial AST27xx SoC device tree</title>
<updated>2026-06-29T19:43:20Z</updated>
<author>
<name>Ryan Chen</name>
<email>ryan_chen@aspeedtech.com</email>
</author>
<published>2026-06-12T09:43:10Z</published>
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<id>urn:sha1:40bf1417bab6363193c0213af011efeb105af2c2</id>
<content type='text'>
Add initial device tree support for the ASPEED AST27xx family, the
8th-generation Baseboard Management Controller (BMC) SoCs.

AST27xx SOC Family
 - https://www.aspeedtech.com/server_ast2700/
 - https://www.aspeedtech.com/server_ast2720/
 - https://www.aspeedtech.com/server_ast2750/

The AST27xx features a dual-SoC architecture consisting of two ties,
referred to as SoC0 and SoC1 - interconnected through an internal
property bus. Both SoCs share the same address decoding scheme,
while each maintains independent clock and reset domains.

- SoC0 (CPU die): contains a dual-core Cortex-A35 cluster and two
  Cortex-M4 cores, along with high-speed peripherals.
- SoC1 (I/O die): includes the BootMCU (responsible for system
  boot) and its own clock/reset domains low-speed peripherals.

The device tree describes the SoC0 and SoC1 domains and their peripheral
layouts.

Signed-off-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>board: toradex: add initial support for aquila imx95</title>
<updated>2026-06-27T02:02:45Z</updated>
<author>
<name>Franz Schnyder</name>
<email>franz.schnyder@toradex.com</email>
</author>
<published>2026-06-11T13:47:48Z</published>
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<id>urn:sha1:3ac3708d168e1f85616817aae077326a6786ab59</id>
<content type='text'>
Add initial U-Boot support for Aquila iMX95 SoM.

Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
Signed-off-by: Franz Schnyder &lt;franz.schnyder@toradex.com&gt;
Reviewed-by: Francesco Dolcini &lt;francesco.dolcini@toradex.com&gt;
</content>
</entry>
<entry>
<title>imx93: Add support for OPTEE</title>
<updated>2026-06-26T20:08:59Z</updated>
<author>
<name>Krzysztof Drobiński</name>
<email>krzysztof@kd-solutions.pl</email>
</author>
<published>2026-06-10T14:17:10Z</published>
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<id>urn:sha1:807b17928a0a95c276ff0f3a17d722faa0057121</id>
<content type='text'>
OPTEE-OS starts correctly when "opteed" is enabled for Secure Payload
Dispatcher in TF-A (tested on OP-TEE version: 4.9.0), however imx93
devices require a patch for OPTEE targets because binman does not see
the tee.bin file when it is available.

Enable conditional OPTEE support for imx93 devices.

Signed-off-by: Krzysztof Drobiński &lt;krzysztof@kd-solutions.pl&gt;
Signed-off-by: Mathieu Dubois-Briand &lt;mathieu.dubois-briand@bootlin.com&gt;
</content>
</entry>
<entry>
<title>imx8m: dts: Update ddr firmware name</title>
<updated>2026-06-26T20:06:15Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2026-06-09T08:36:24Z</published>
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<id>urn:sha1:fd1072d0d59f5afaf7d0f258cfead16558be6ca9</id>
<content type='text'>
Update to latest ddr firmware name, otherwise user may use legacy ddr
firmware from linux-firmware-imx release.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx952: Update gpio node regs</title>
<updated>2026-06-26T20:00:22Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2026-06-09T08:36:19Z</published>
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<id>urn:sha1:f59da150c9aa751a3b93691b21872bd427be637c</id>
<content type='text'>
Same to 85319b2e672 ("board: toradex: smarc-imx95: remove gpio1 reg"),
there is no need to use dual base for i.MX952 gpio, so drop the U-Boot
specific reg changes.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2026.07-rc5' into next</title>
<updated>2026-06-22T22:42:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-06-22T22:42:41Z</published>
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<id>urn:sha1:9f16b258e5632d74fa4a1c2c93bea4474e05234b</id>
<content type='text'>
Prepare v2026.07-rc5
</content>
</entry>
<entry>
<title>Merge patch series "arm: omap: Add back omap4 support"</title>
<updated>2026-06-17T15:52:33Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-06-17T15:52:33Z</published>
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<id>urn:sha1:e79de74103d9d411aa6b4e63582c5d7075c6a7a8</id>
<content type='text'>
Bastien Curutchet &lt;bastien.curutchet@bootlin.com&gt; says:

This series aims to add back the omap4 support. This support was removed
by commit b0ee3fe642c ("arm: ti: Remove omap4 platform support") because
at that moment, none of the OMAP4-based boards had done the migration to
DM_I2C.
My use case is an old product based on the Variscite's omap4 system on
module. I needed to upgrade U-Boot on it for security reasons. I think
that this work could benefit to other people who may have same kind of
product to maintain.

Patch 1 to 3 remove the omap's clock driver dependency to the AM33xx
as it is also present in omap4 platforms. I tested these changes on the
beaglebone black to ensure I didn't break the AM33xx case.

Patch 4 &amp; 5 revert the deletion of the omap4 support. The revert makes
checkpatch.pl angry. I fixed quite a lots of warnings already but it
remains two kinds of warnings:
- CamelCase on timings structure, I left the CamelCase because IMHO it's
  more readable this way.
- #ifdef CONFIG_XYZ shouldn't be used anymore. I left one of this because
  I didn't find a clean way to get rid of it.

Patch 6 adds support for the Variscite's system on module. This system on
module is supported by the Linux project through
ti/omap/omap4-var-som-om44.dtsi

Link: https://lore.kernel.org/r/20260608-omap4-support-v3-0-8595ccd203f0@bootlin.com
</content>
</entry>
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