u-boot.git/arch/arm/imx-common/cache.c, branch v2016.09Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/arch/arm/imx-common/cache.c?h=v2016.092016-05-06T14:43:39Zimx6: cache: disable L2 before touching Auxiliary Control Register2016-05-06T14:43:39ZPeng Fanpeng.fan@nxp.com2016-05-04T07:27:50Zurn:sha1:ad7af5d7e4caf49581c7403d5a8edc0f11a5f652
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"
So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
arm: imx: common rework cache settings for imx62015-09-13T08:11:53ZAdrian Alonsoaalonso@freescale.com2015-09-02T18:54:14Zurn:sha1:ab09e728667563fda9c8a8569331618fcfa0cb16
Rework cache settings for imx6, move cache configuration
to imx-common/cache.c so it can be reused for newer SoC
Signed-off-by: Adrian Alonso <aalonso@freescale.com>