u-boot.git/arch/arm/include/asm/arch-aspeed/platform.h, branch master Unnamed repository; edit this file 'description' to name the repository. aspeed: ast2600: Enlarge SRAM size 2021-11-17T22:04:59+00:00 Chia-Wei Wang chiawei_wang@aspeedtech.com 2021-10-27T06:17:25+00:00 3d99be97f1193c6b08f1498f02f390d4884af3d1 The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> 
The AST2600 SRAM has been extended to 88KB since A1
chip revision. This patch updates the SRAM size to
offer more space for early stack/heap use.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
aspeed: Add AST2600 platform support 2021-01-18T20:23:06+00:00 Chia-Wei, Wang chiawei_wang@aspeedtech.com 2020-12-14T05:54:28+00:00 4a84cf06aa05b10b31b876e6d6f43168945213af Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> 
Add low level platform initialization for the AST2600 SoC.
The 2-stage booting with U-Boot SPL are leveraged to support
different booting mode.

However, currently the patch supports only the booting from
memory-mapped SPI flash.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
include/configs: aspeed: Remove hardcoded variables 2020-08-14T13:46:40+00:00 Chia-Wei, Wang chiawei_wang@aspeedtech.com 2020-08-03T09:36:08+00:00 98ef128b56b84249f05a840d24a079ec9baef814 The hardcoded platform variables such as DRAM base address are not common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces those hardcoded with macros defined in a newly added header, where the basic SoC HW information are assigned accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> 
The hardcoded platform variables such as DRAM base address are not
common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces
those hardcoded with macros defined in a newly added header, where
the basic SoC HW information are assigned accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>