ram: aspeed: add SDRAM controller driver for AST2700

2026-06-29T19:43:21Z

Add a SDRAM controller driver for the AST2700, derived from the existing AST2700 controller code used by the Ibex SPL but adapted to run from ARM U-Boot proper on the Cortex-A35 cores. The DDR4/DDR5 controller and its DesignWare PHY are programmed by the Ibex SPL before ARM U-Boot proper takes over. This driver reads back the configuration left by the SPL, probes the controller, and exposes ram_info (base and size, with the VGA carve-out subtracted) via UCLASS_RAM so that dram_init() can populate gd->ram_size. The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*) are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub when ARM U-Boot proper is the caller; the real implementation is provided by the Ibex SPL via the same fmc_hdr.h descriptor format (here added for the ARM build). Adds the supporting register-layout headers under arch/arm/include/asm/arch-aspeed/: - sdram.h: SDRAM controller and DWC PHY register definitions - scu.h: SCU bits referenced by the SDRAM driver - fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used by the Ibex SPL) Signed-off-by: Ryan Chen

u-boot.git/arch/arm/include/asm/arch-aspeed/sdram.h, branch master

ram: aspeed: add SDRAM controller driver for AST2700