<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/include/asm/arch-aspeed, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-aspeed?h=master</id>
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<updated>2026-06-29T19:43:21Z</updated>
<entry>
<title>ram: aspeed: add SDRAM controller driver for AST2700</title>
<updated>2026-06-29T19:43:21Z</updated>
<author>
<name>Ryan Chen</name>
<email>ryan_chen@aspeedtech.com</email>
</author>
<published>2026-06-12T09:43:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4a72fd9fb09109857303ca64fd259009e1d4b554'/>
<id>urn:sha1:4a72fd9fb09109857303ca64fd259009e1d4b554</id>
<content type='text'>
Add a SDRAM controller driver for the AST2700, derived from the
existing AST2700 controller code used by the Ibex SPL but adapted
to run from ARM U-Boot proper on the Cortex-A35 cores.

The DDR4/DDR5 controller and its DesignWare PHY are programmed by
the Ibex SPL before ARM U-Boot proper takes over. This driver
reads back the configuration left by the SPL, probes the
controller, and exposes ram_info (base and size, with the VGA
carve-out subtracted) via UCLASS_RAM so that dram_init() can
populate gd-&gt;ram_size.

The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*)
are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub
when ARM U-Boot proper is the caller; the real implementation is
provided by the Ibex SPL via the same fmc_hdr.h descriptor format
(here added for the ARM build).

Adds the supporting register-layout headers under
arch/arm/include/asm/arch-aspeed/:
  - sdram.h:   SDRAM controller and DWC PHY register definitions
  - scu.h:     SCU bits referenced by the SDRAM driver
  - fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with
               arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used
               by the Ibex SPL)

Signed-off-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>arm: aspeed: add ASPEED AST2700 SoC family support</title>
<updated>2026-06-29T19:43:20Z</updated>
<author>
<name>Ryan Chen</name>
<email>ryan_chen@aspeedtech.com</email>
</author>
<published>2026-06-12T09:43:09Z</published>
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<id>urn:sha1:b62b55ba4b2d1cabd6bb0943685c3115f6ee8bd3</id>
<content type='text'>
Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35)
Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th
generation BMC and uses a dual-die architecture: SoC0 (the "CPU"
die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000,
while SoC1 (the "IO" die) hosts the peripherals and its own SCU at
0x14c02000.

This commit adds:
  - ASPEED_AST2700 Kconfig option and the ast2700 mach subdir
    (mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*)
  - arm64 MMU map covering the SoC device window and the DRAM
    region at 0x4_0000_0000 (up to 8 GiB)
  - lowlevel_init.S for early CPU bring-up
  - cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants)
    and reset cause (cold reset, EXT reset, WDT reset)
  - board_common: dram_init via UCLASS_RAM, AHBC timeout init
  - platform: env_get_location() that selects SPI/eMMC based on
    the IO-die HW strap; arch_misc_init() that exposes
    ${boot_device} and ${verify} to the boot script
  - SCU0/SCU1 register layout header (scu_ast2700.h)
  - configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h
    for the AST2700 EVB board

The defconfig depends on ast2700-evb.dts, which is introduced in
a subsequent patch; this commit must be applied with the
remaining series for evb-ast2700_defconfig to build.

Signed-off-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03Z</published>
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<id>urn:sha1:03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43Z</published>
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<id>urn:sha1:d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: aspeed: Add missing &lt;linux/types.h&gt;</title>
<updated>2024-05-07T14:00:40Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-02T01:30:19Z</published>
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<id>urn:sha1:5f5d57869a7ad9d0d7d75f6c067c11de0f1ecac4</id>
<content type='text'>
The scu* files have many "Linux" style types in them, add
&lt;linux/types.h&gt;

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ram: ast2600: Align the RL and WL setting</title>
<updated>2022-11-24T21:26:01Z</updated>
<author>
<name>Dylan Hung</name>
<email>dylan_hung@aspeedtech.com</email>
</author>
<published>2022-11-11T07:30:08Z</published>
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<id>urn:sha1:8c7b55724c6f9deb6d8a291cba7f932373313b57</id>
<content type='text'>
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Review-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
Signed-off-by: Dylan Hung &lt;dylan_hung@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>ast2600: spl: Add boot mode detection</title>
<updated>2022-06-23T01:30:05Z</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2022-06-01T08:43:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=12770d0df0e841cfa1bdbde7636aad3d531bf66b'/>
<id>urn:sha1:12770d0df0e841cfa1bdbde7636aad3d531bf66b</id>
<content type='text'>
AST2600 supports boot from SPI(mmap), eMMC, and UART.
This patch adds the boot mode detection and return the
corresponding boot device type.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>doc: replace @return by Return:</title>
<updated>2022-01-19T17:11:34Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2022-01-19T17:05:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=185f812c419f1b4f0d10d9787d59cf9f11a2a600'/>
<id>urn:sha1:185f812c419f1b4f0d10d9787d59cf9f11a2a600</id>
<content type='text'>
Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
</entry>
<entry>
<title>clk: ast2600: Add RSACLK control for ACRY</title>
<updated>2021-11-17T22:05:00Z</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2021-10-27T06:17:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=af6451187c2b93a05a03ca6e9f4f33cabf6da04a'/>
<id>urn:sha1:af6451187c2b93a05a03ca6e9f4f33cabf6da04a</id>
<content type='text'>
Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine
of ASPEED AST2600 SoCs.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>clk: ast2600: Add YCLK control for HACE</title>
<updated>2021-11-17T22:05:00Z</updated>
<author>
<name>Joel Stanley</name>
<email>joel@jms.id.au</email>
</author>
<published>2021-10-27T06:17:26Z</published>
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<id>urn:sha1:4080714f5ee9253715ce72ebb4da4a02f4a9b3a0</id>
<content type='text'>
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.

Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</content>
</entry>
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