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<title>u-boot.git/arch/arm/include/asm/arch-davinci/hardware.h, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-davinci/hardware.h?h=main</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-davinci/hardware.h?h=main'/>
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<updated>2015-02-21T13:23:52Z</updated>
<entry>
<title>ARM: davinci: move SoC headers to mach-davinci/include/mach</title>
<updated>2015-02-21T13:23:52Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2015-02-20T08:04:14Z</published>
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<id>urn:sha1:3d357619a509eb2b39dc5056731ca08bc2b23e62</id>
<content type='text'>
Move arch/arm/include/asm/arch-davinci/*
  -&gt; arch/arm/mach-davinci/include/mach/*

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: davinci: add header file for driver definitions</title>
<updated>2014-06-19T21:53:58Z</updated>
<author>
<name>Khoronzhuk, Ivan</name>
<email>ivan.khoronzhuk@ti.com</email>
</author>
<published>2014-06-07T01:22:52Z</published>
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<id>urn:sha1:3e01ed00da98a29fe2b71c6d60309d5b09adc0de</id>
<content type='text'>
The definitions inside emif_defs.h concern davinci nand driver and
should be in it's header. So create header file for davinci nand
driver and move definitions from emif_defs.h and nand_defs.h to it.

Acked-by: Vitaly Andrianov &lt;vitalya@ti.com&gt;
Signed-off-by: Ivan Khoronzhuk &lt;ivan.khoronzhuk@ti.com&gt;
[trini: Fixup more davinci breakage]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>sizes.h - consolidate for all architectures</title>
<updated>2014-03-04T17:15:01Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>Alexey.Brodkin@synopsys.com</email>
</author>
<published>2014-02-26T13:47:58Z</published>
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<id>urn:sha1:1ace4022394eacbdae12e7275c445699f8ad4833</id>
<content type='text'>
Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;

Cc: Vineet Gupta &lt;vgupta@synopsys.com&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Acked-by: Tom Rini &lt;trini@ti.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>davinci: fix Master Priority Registers location</title>
<updated>2013-12-04T16:41:13Z</updated>
<author>
<name>Viktar Palstsiuk</name>
<email>viktar.palstsiuk@promwad.com</email>
</author>
<published>2013-11-26T11:30:26Z</published>
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<id>urn:sha1:3558243b6fc80b14a6281bd0e2792672b462684c</id>
<content type='text'>
MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at
0x01C14114

Signed-off-by: Viktar Palstsiuk &lt;viktar.palstsiuk@promwad.com&gt;
</content>
</entry>
<entry>
<title>am33xx, davinci: Create and use &lt;asm/davinci_rtc.h&gt;</title>
<updated>2013-11-01T19:30:22Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2013-08-28T13:00:28Z</published>
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<id>urn:sha1:155d424a9a0228e2f38ce21a92b20c31896d61d2</id>
<content type='text'>
Create a common header file for the RTC IP block that is shared between
davinci and am33xx.

Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>da850: provide davinci_enable_uart0</title>
<updated>2013-05-10T12:25:56Z</updated>
<author>
<name>Eric Benard</name>
<email>eric@eukrea.com</email>
</author>
<published>2013-04-22T05:54:59Z</published>
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<id>urn:sha1:81ac7e51ccf2984e9c0964a883d6b7e8fe875aad</id>
<content type='text'>
this is needed to bring UART0 out of reset but this function
currently only exists for dm644x/355/365/646x when da850 (at
least am1808 also need it).

Signed-off-by: Eric Bénard &lt;eric@eukrea.com&gt;
</content>
</entry>
<entry>
<title>da8xx/hawkboard: Add support for ohci host controller</title>
<updated>2012-09-01T12:58:19Z</updated>
<author>
<name>Sughosh Ganu</name>
<email>urwithsughosh@gmail.com</email>
</author>
<published>2012-08-09T10:45:20Z</published>
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<id>urn:sha1:25f8bf6eff9e66df850301c5e9e5259807e286f0</id>
<content type='text'>
Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.

Move the usb header for da8xx platforms under arch-davinci.

Signed-off-by: Sughosh Ganu &lt;urwithsughosh@gmail.com&gt;
</content>
</entry>
<entry>
<title>DaVinci DA8xx: replace magic number for DDR speed</title>
<updated>2012-09-01T12:58:14Z</updated>
<author>
<name>Laurence Withers</name>
<email>lwithers@guralp.com</email>
</author>
<published>2012-07-30T23:30:36Z</published>
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<id>urn:sha1:de9d2e3d60dba1ab775ad67032b5afa00086f53f</id>
<content type='text'>
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).

Signed-off-by: Laurence Withers &lt;lwithers@guralp.com&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Prabhakar Lad &lt;prabhakar.csengg@gmail.com&gt;
</content>
</entry>
<entry>
<title>DaVinci DA850: UART2 clock ID comes from ASYNC3</title>
<updated>2012-09-01T12:58:14Z</updated>
<author>
<name>Laurence Withers</name>
<email>lwithers@guralp.com</email>
</author>
<published>2012-07-30T23:30:35Z</published>
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<id>urn:sha1:88ac6b9d1402b5a7b639131df95bdd2dbd54d69d</id>
<content type='text'>
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.

Signed-off-by: Laurence Withers &lt;lwithers@guralp.com&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Prabhakar Lad &lt;prabhakar.csengg@gmail.com&gt;
</content>
</entry>
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