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<title>u-boot.git/arch/arm/include/asm/arch-exynos/clock.h, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-exynos/clock.h?h=main</id>
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<updated>2015-08-17T04:06:52Z</updated>
<entry>
<title>ARM: exynos: move SoC sources to mach-exynos</title>
<updated>2015-08-17T04:06:52Z</updated>
<author>
<name>Thomas Abraham</name>
<email>thomas.ab@samsung.com</email>
</author>
<published>2015-08-03T12:28:00Z</published>
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<id>urn:sha1:77b55e8cfcee9ce1a973bf4dad3e160dd0be01f3</id>
<content type='text'>
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow
reuse of existing code for ARMv8 based Exynos platforms.

Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Signed-off-by: Thomas Abraham &lt;thomas.ab@samsung.com&gt;
Reviewed-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Tested-by: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Acked-by: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>Exynos5420: Add clock initialization for 5420</title>
<updated>2013-12-30T07:50:34Z</updated>
<author>
<name>Rajeshwari Birje</name>
<email>rajeshwari.s@samsung.com</email>
</author>
<published>2013-12-26T04:14:21Z</published>
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<id>urn:sha1:060c227a2861b0702e34eabe08eea9cc5bb68b45</id>
<content type='text'>
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420

Signed-off-by: Rajeshwari S Shinde &lt;rajeshwari.s@samsung.com&gt;
Signed-off-by: Akshay Saraswat &lt;akshay.s@samsung.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>ARM: Added I2S0 clocks for audio</title>
<updated>2013-09-24T13:10:33Z</updated>
<author>
<name>Dani Krishna Mohan</name>
<email>krishna.md@samsung.com</email>
</author>
<published>2013-09-11T11:08:48Z</published>
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<id>urn:sha1:3dd22a37aae57243b6e8dfedcc03c0fc02d469e6</id>
<content type='text'>
This patch makes the necessary changes for making use of
I2S0 channel instead of I2S1 channel on smdk board. This
changes are done to maintain the uniformity to use I2S0 channel.

Signed-off-by: Dani Krishna Mohan &lt;krishna.md@samsung.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12</title>
<updated>2012-12-26T07:16:02Z</updated>
<author>
<name>Chander Kashyap</name>
<email>chander.kashyap@linaro.org</email>
</author>
<published>2012-12-25T20:13:40Z</published>
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<id>urn:sha1:07235ef8a377937f3ddc71b2bd259658c8c40c6b</id>
<content type='text'>
This patch adds clock structure for Exynos4x12.

Signed-off-by: Chander Kashyap &lt;chander.kashyap@linaro.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>EXYNOS: Add clock for I2S</title>
<updated>2012-11-15T12:08:20Z</updated>
<author>
<name>Rajeshwari Shinde</name>
<email>rajeshwari.s@samsung.com</email>
</author>
<published>2012-10-25T19:49:29Z</published>
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<id>urn:sha1:2e206caaa658342148ac0c7d869da3426414b14d</id>
<content type='text'>
This patch adds clock support for I2S

Signed-off-by: R. Chandrasekar &lt;rcsekar@samsung.com&gt;
Signed-off-by: Rajeshwari Shinde &lt;rajeshwari.s@samsung.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>EXYNOS5: CLOCK: Add BPLL support</title>
<updated>2012-09-01T12:58:23Z</updated>
<author>
<name>Rajeshwari Shinde</name>
<email>rajeshwari.s@samsung.com</email>
</author>
<published>2012-07-03T20:02:58Z</published>
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<id>urn:sha1:10bc1a7f49b2efec3eddca18949d28ad053f40bb</id>
<content type='text'>
This patch adds support for BPLL clock.

Signed-off-by: Rajeshwari Shinde &lt;rajeshwari.s@samsung.com&gt;
Acked-by: Joonyoung Shim &lt;jy0922.shim@samsung.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0</title>
<updated>2012-09-01T12:58:23Z</updated>
<author>
<name>Rajeshwari Shinde</name>
<email>rajeshwari.s@samsung.com</email>
</author>
<published>2012-07-03T20:02:57Z</published>
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<id>urn:sha1:6071bcaec1cbbdd2679f9abdd36dfe16114bc315</id>
<content type='text'>
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali &lt;hatim.rv@samsung.com&gt;
Signed-off-by: Rajeshwari Shinde &lt;rajeshwari.s@samsung.com&gt;
Acked-by: Joonyoung Shim &lt;jy0922.shim@samsung.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0</title>
<updated>2012-09-01T12:58:23Z</updated>
<author>
<name>Rajeshwari Shinde</name>
<email>rajeshwari.s@samsung.com</email>
</author>
<published>2012-07-03T20:02:54Z</published>
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<id>urn:sha1:526b57069920c5597e14b7730f1a81df716d99ce</id>
<content type='text'>
Define additional registers for clock control in Exynos5250 Rev 1.0

Signed-off-by: Hatim Ali &lt;hatim.rv@samsung.com&gt;
Signed-off-by: Rajeshwari Shinde &lt;rajeshwari.s@samsung.com&gt;
Acked-by: Joonyoung Shim &lt;jy0922.shim@samsung.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>ARM: EXYNOS: Add support for Exynos5 based SoCs</title>
<updated>2012-02-12T09:11:30Z</updated>
<author>
<name>Chander Kashyap</name>
<email>chander.kashyap@linaro.org</email>
</author>
<published>2012-02-05T23:01:46Z</published>
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<id>urn:sha1:37bb6d89de399a6fc2aa0905452dd780e15e9900</id>
<content type='text'>
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.

Signed-off-by: Chander Kashyap &lt;chander.kashyap@linaro.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
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