u-boot.git/arch/arm/include/asm/arch-exynos, branch master

ARM: exynos: move SoC sources to mach-exynos

2015-08-17T04:06:52Z

Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang Cc: Albert Aribaud Cc: Masahiro Yamada Signed-off-by: Thomas Abraham Reviewed-by: Masahiro Yamada Tested-by: Przemyslaw Marczak Acked-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang

exynos: video: Remove non-device-tree code

2015-08-06T03:06:17Z

We always use device tree on exynos, so remove the unused code. Signed-off-by: Simon Glass

exynos: Add support for the DisplayPort hotplug detect

2015-08-06T03:06:14Z

Allow this function to be selected using the pinmux API. Signed-off-by: Simon Glass

arm: exynos: USB3 PHY base definition for Exynos5 SoCs

2015-06-08T13:25:41Z

After that change it would be possible to call samsung_get_base_usb3_phy() function to get proper base address Signed-off-by: Lukasz Majewski Cc: Minkyu Kang

arm: exynos: add display clocks for Exynos5800

2015-04-06T05:34:40Z

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang

Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800

2015-02-28T09:03:46Z

It was found that the L2 cache timings that we had before could cause freezes and hangs. We should make things more robust with better timings. Currently the production ChromeOS kernel applies these timings, but it's nice to fixup firmware too (and upstream probably won't take our kernel hacks). This also provides a big cleanup of the L2 cache init code avoiding some duplication. The way things used to work: * low_power_start() was installed by the SPL (both at boot and resume time) and left resident in iRAM for the kernel to use when bringing up additional CPUs. It used configure_l2_ctlr() and configure_l2_actlr() when it detected it was on an A15. This was needed (despite the L2 cache registers being shared among all A15s) because we might have been the first man in after the whole A15 cluster was shutdown. * secondary_cores_configure() was called on at boot time and at resume time. Strangely this called configure_l2_ctlr() but not configure_l2_actlr() which was almost certainly wrong. Given that we'll call both (see next bullet) later in the boot process it didn't matter for normal boot, but I guess this is how L2 cache settings got set on 5420/5800 (but not 5250?) at resume time. * exynos5_set_l2cache_params() was called as part of cache enablement. This should happen at boot time (normally in the SPL except for USB boot where it happens in main U-Boot). Note that the old code wasn't setting ECC/parity in the cache enablement code but we happened to get it anyway because we'd call secondary_cores_configure() at boot time. For resume time we'd get it anyway when the 2nd A15 core came up. Let's make this a whole lot simpler. Now we always set these parameters in the same place for all boots and use the same code for setting up secondary CPUs. Intended net effects of this change (other than cleanup): * Timings go from before: data: 0 cycle setup, 3 cycles (0x2) latency tag: 0 cycle setup, 3 cycles (0x2) latency after: data: 1 cycle setup, 4 cycles (0x3) latency tag: 1 cycle setup, 4 cycles (0x3) latency * L2ACTLR is properly initted on 5420/5800 in all cases. One note is that we're still relying on luck to keep low_power_start() working. The compiler is being nice and not storing anything on the stack. Another note is that on its own this patch won't help to fix cache settings in an RW U-Boot update where we still have the RO SPL. The plan for that is: * Have RW U-Boot re-init the cache right before calling the kernel (after it has turned the L2 cache off). This is why the functions are in a header file instead of lowlevel_init.c. * Have the kernel save the L2 cache settings of the boot CPU and apply them to all other CPUs. We get a little lucky here because the old code was using "|=" to modify the registers and all of the bits that it's setting are also present in the new settings (!). That means that when the 2nd CPU in the A15 cluster comes up it doesn't actually mess up the settings of the 1st CPU in the A15 cluster. An alternative option is to have the kernel write its own low_power_start() code. Signed-off-by: Doug Anderson Signed-off-by: Akshay Saraswat Signed-off-by: Minkyu Kang

Exynos542x: Fix secondary core booting for thumb

2015-02-28T09:03:46Z

When compiled SPL for Thumb secondary cores failed to boot at the kernel boot up. Only one core came up out of 4. This was happening because the code relocated to the address 0x02073000 by the primary core was an ARM asm code which was executed by the secondary cores as if it was a thumb code. This patch fixes the issue of secondary cores considering relocated code as Thumb instructions and not ARM instructions by jumping to the relocated with the help of "bx" ARM instruction. "bx" instruction changes the 5th bit of CPSR which allows execution unit to consider the following instructions as ARM instructions. Signed-off-by: Akshay Saraswat Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang

Exynos542x: CPU: Power down all secondary cores

2015-02-28T09:03:46Z

This patch adds code to shutdown secondary cores. When U-boot comes up, all secondary cores appear powered on, which is undesirable and causes side effects while initializing these cores in kernel. Secondary core power down happens in following steps: Step-1: After Exynos power-on, primary core starts executing first. Step-2: In iROM code every core has to check 2 flags i.e. addresses 0x02020028 & 0x02020004. Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a jump address for primary core and 0 for all secondary cores. Step-4: Therefore, primary core follows normal iROM execution and jumps to BL1 eventually, whereas all secondary cores enter WFE. Step-5: When primary core comes into function secondary_cores_configure, it puts pointer to function power_down_core into 0x02020004 and provides DSB and SEV for all cores so that they may come out of WFE and jump to power_down_core function. Step-6: And ultimately because of power_down_core all secondary cores shut-down. Signed-off-by: Kimoon Kim Signed-off-by: Akshay Saraswat Signed-off-by: Minkyu Kang

Exynos542x: Add and enable get_periph_rate support

2015-02-13T08:23:06Z

We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800. Signed-off-by: Akshay Saraswat Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang

exynos5: pinmux: check flag for i2c config

2015-01-30T00:10:00Z

Some versions of Exynos5 supports High-Speed I2C, on few interfaces, this change allows support this. The new flag is: PINMUX_FLAG_HS_MODE Signed-off-by: Przemyslaw Marczak Cc: Simon Glass Cc: Akshay Saraswat Cc: Minkyu Kang Acked-by: Simon Glass