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<title>u-boot.git/arch/arm/include/asm/arch-ls102xa, branch v2016.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-ls102xa?h=v2016.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-ls102xa?h=v2016.01'/>
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<updated>2015-12-15T00:57:32Z</updated>
<entry>
<title>armv7/fsl-ls102xa: Workaround for DDR erratum A008514</title>
<updated>2015-12-15T00:57:32Z</updated>
<author>
<name>Yao Yuan</name>
<email>yao.yuan@freescale.com</email>
</author>
<published>2015-12-05T06:59:13Z</published>
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<id>urn:sha1:6c4a1eba3fcc013f7d21cdb88098bdd3e7afa75b</id>
<content type='text'>
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao &lt;yao.yuan@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm: ls102xa: enable all the snoop signal for masters.</title>
<updated>2015-12-14T02:27:29Z</updated>
<author>
<name>Yao Yuan</name>
<email>yao.yuan@freescale.com</email>
</author>
<published>2015-12-05T06:59:11Z</published>
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<id>urn:sha1:762b3535467202ee216dce81f13eec42cd2ac2e3</id>
<content type='text'>
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao &lt;yao.yuan@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm: ls1021a: merge SoC specific code in a separate file</title>
<updated>2015-12-14T02:27:29Z</updated>
<author>
<name>Yao Yuan</name>
<email>yao.yuan@freescale.com</email>
</author>
<published>2015-12-05T06:59:10Z</published>
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<id>urn:sha1:7ba0261810dd8924f0aeeb4cf2f12253106170b3</id>
<content type='text'>
Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao &lt;yao.yuan@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm: ls102x: add get_svr and IS_SVR_REV helper</title>
<updated>2015-12-14T02:27:28Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2015-11-20T07:52:02Z</published>
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<id>urn:sha1:0c028a03284aabceb89a85736e23661d6fe7915e</id>
<content type='text'>
Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit</title>
<updated>2015-11-30T16:53:01Z</updated>
<author>
<name>Alison Wang</name>
<email>b18965@freescale.com</email>
</author>
<published>2015-07-15T07:13:05Z</published>
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<id>urn:sha1:2b714cfad4bb75e9be394de36929ef5c79ce17bb</id>
<content type='text'>
This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot.  Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.  This causes the timer compare to fire 344 seconds
after u-boot configures it.  Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains.  Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour &lt;techie@whiterocker.com&gt;
Signed-off-by: Alison Wang &lt;alison.wang@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm: ls1021a: Add sata support on qds and twr board</title>
<updated>2015-10-29T17:34:02Z</updated>
<author>
<name>tang yuantian</name>
<email>Yuantian.Tang@freescale.com</email>
</author>
<published>2015-10-16T08:06:05Z</published>
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<id>urn:sha1:4632ad773ed31f4dd6aeb859de148402f8932111</id>
<content type='text'>
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian &lt;Yuantian.Tang@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>armv7/ls1021a: move ns_access to common file</title>
<updated>2015-10-29T17:33:58Z</updated>
<author>
<name>Mingkai Hu</name>
<email>Mingkai.Hu@freescale.com</email>
</author>
<published>2015-10-26T11:47:41Z</published>
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<id>urn:sha1:435acd83b2b4f31699732f090d28d66cabb05912</id>
<content type='text'>
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Signed-off-by: Hou Zhiqiang &lt;B48286@freescale.com&gt;
Signed-off-by: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm: ls102xa: enable snooping for CAAM transactions</title>
<updated>2015-10-29T17:33:58Z</updated>
<author>
<name>horia.geanta@freescale.com</name>
<email>horia.geanta@freescale.com</email>
</author>
<published>2015-10-15T11:21:31Z</published>
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<id>urn:sha1:5757e06c69a02fe95208a503504756b7d422e64f</id>
<content type='text'>
Enable snooping for CAAM read &amp; write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]

Signed-off-by: Horia Geantă &lt;horia.geanta@freescale.com&gt;
Reviewed-by: Zhengxiong Jin &lt;Jason.Jin@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm/ls102xa:add hwconfig setting to support disable unused devices</title>
<updated>2015-09-02T02:49:20Z</updated>
<author>
<name>Zhuoyu Zhang</name>
<email>Zhuoyu.Zhang@freescale.com</email>
</author>
<published>2015-08-17T10:55:12Z</published>
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<id>urn:sha1:03c22449c5b7daff0a43291b34564a52660b83b8</id>
<content type='text'>
DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.

For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma"
in hwconfig, thus ESDHC controller &amp; eDMA/qDMA will be clock gated to
save more power.

Signed-off-by: Zhuoyu Zhang &lt;Zhuoyu.Zhang@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>ls102xa: etsec: Use proper settings for BE BDs</title>
<updated>2015-09-02T02:39:03Z</updated>
<author>
<name>Claudiu Manoil</name>
<email>claudiu.manoil@freescale.com</email>
</author>
<published>2015-08-12T10:29:14Z</published>
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<id>urn:sha1:ebe4c1e6469444753bd2ba93fe63e6183cf2905c</id>
<content type='text'>
Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.

Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil &lt;claudiu.manoil@freescale.com&gt;
Acked-by: Alison Wang &lt;alison.wang@freescale.com&gt;
Tested-by: Alison Wang &lt;alison.wang@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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