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<title>u-boot.git/arch/arm/include/asm/arch-ls102xa, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-ls102xa?h=v2016.09</id>
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<updated>2016-08-26T21:04:46Z</updated>
<entry>
<title>ARM: Move SYS_CACHELINE_SIZE over to Kconfig</title>
<updated>2016-08-26T21:04:46Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-22T12:22:17Z</published>
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<id>urn:sha1:067716bac59716b07f1ee70d9bf6e5528289bb45</id>
<content type='text'>
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Prafulla Wadaskar &lt;prafulla@marvell.com&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Steve Rae &lt;steve.rae@raedomain.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: "Pali Rohár" &lt;pali.rohar@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Grazvydas Ignotas &lt;notasas@gmail.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: David Feng &lt;fenghua@phytium.com.cn&gt;
Cc: Alison Wang &lt;b18965@freescale.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Cc: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Cc: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Cc: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Cc: Saksham Jain &lt;saksham.jain@nxp.com&gt;
Cc: Qianyu Gong &lt;qianyu.gong@nxp.com&gt;
Cc: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Cc: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Cc: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Cc: tang yuantian &lt;Yuantian.Tang@freescale.com&gt;
Cc: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
Cc: Josh Wu &lt;josh.wu@atmel.com&gt;
Cc: Bo Shen &lt;voice.shen@atmel.com&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Christophe Ricard &lt;christophe-h.ricard@st.com&gt;
Cc: Anand Moon &lt;linux.amoon@gmail.com&gt;
Cc: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Cc: Carlo Caione &lt;carlo@endlessm.com&gt;
Cc: huang lin &lt;hl@rock-chips.com&gt;
Cc: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Cc: Xu Ziyuan &lt;xzy.xu@rock-chips.com&gt;
Cc: "jk.kernel@gmail.com" &lt;jk.kernel@gmail.com&gt;
Cc: "Ariel D'Alessandro" &lt;ariel@vanguardiasur.com.ar&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Cc: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Cc: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Andre Przywara &lt;andre.przywara@arm.com&gt;
Cc: Bernhard Nortmann &lt;bernhard.nortmann@web.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Alexander Graf &lt;agraf@suse.de&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Vitaly Andrianov &lt;vitalya@ti.com&gt;
Cc: "Andrew F. Davis" &lt;afd@ti.com&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Carlos Hernandez &lt;ceh@ti.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Cc: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Chin Liang See &lt;clsee@altera.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</content>
</entry>
<entry>
<title>ARMv7: PSCI: ls102xa: move secure text section into OCRAM</title>
<updated>2016-07-26T16:03:00Z</updated>
<author>
<name>Hongbo Zhang</name>
<email>hongbo.zhang@nxp.com</email>
</author>
<published>2016-07-21T10:09:39Z</published>
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<id>urn:sha1:3288628a8d23681c865e91e65a341d48eb5fed73</id>
<content type='text'>
LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Signed-off-by: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention</title>
<updated>2016-07-26T16:02:49Z</updated>
<author>
<name>Hongbo Zhang</name>
<email>hongbo.zhang@nxp.com</email>
</author>
<published>2016-07-21T10:09:38Z</published>
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<id>urn:sha1:aeb901f2a6c19e399354345ad1acd67420401a10</id>
<content type='text'>
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
    psci_version,
    psci_features,
    psci_cpu_suspend,
    psci_affinity_info,
    psci_system_reset,
    psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Signed-off-by: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>include: usb: Rename USB controller base address mapping</title>
<updated>2016-07-26T16:01:04Z</updated>
<author>
<name>Rajesh Bhagat</name>
<email>rajesh.bhagat@nxp.com</email>
</author>
<published>2016-06-07T13:29:34Z</published>
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<id>urn:sha1:9729dc9565c9c1812efbb630e1db4d54f580363c</id>
<content type='text'>
Remove Soc specific defines and use generic chasis specific defines
for USB controller base address mapping.

Signed-off-by: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-05-24T17:42:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-05-24T17:42:03Z</published>
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<id>urn:sha1:fc15b9beed05dec6cc092c265042381a0eadb0e9</id>
<content type='text'>
</content>
</entry>
<entry>
<title>arch/arm, arch/powerpc: add # of SEC engines on the SOC</title>
<updated>2016-05-18T15:51:46Z</updated>
<author>
<name>Alex Porosanu</name>
<email>alexandru.porosanu@freescale.com</email>
</author>
<published>2016-04-29T12:17:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=404bf4547ecb4c1409ae0936444fe02ba978e510'/>
<id>urn:sha1:404bf4547ecb4c1409ae0936444fe02ba978e510</id>
<content type='text'>
Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.

Signed-off-by: Alex Porosanu &lt;alexandru.porosanu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: add SEC JR0 offset</title>
<updated>2016-05-18T15:51:46Z</updated>
<author>
<name>Alex Porosanu</name>
<email>alexandru.porosanu@freescale.com</email>
</author>
<published>2016-04-29T12:17:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e99d7193593cf6331ea04cd394a9a4cf18886ef0'/>
<id>urn:sha1:e99d7193593cf6331ea04cd394a9a4cf18886ef0</id>
<content type='text'>
Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)

Signed-off-by: Alex Porosanu &lt;alexandru.porosanu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSI</title>
<updated>2016-05-17T15:54:43Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-01T17:36:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c649e3c91cdc96a86ca2665fcfafaca5c4b384b1'/>
<id>urn:sha1:c649e3c91cdc96a86ca2665fcfafaca5c4b384b1</id>
<content type='text'>
This option currently enables both the command and the SCSI functionality.
Rename the existing option to CONFIG_SCSI since most of the code relates
to the feature.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>configs: Re-sync with cmd/Kconfig</title>
<updated>2016-04-25T19:09:47Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-04-24T21:29:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=89cb2b5f8be4f6d04bd87220aa8f72eb0850edc4'/>
<id>urn:sha1:89cb2b5f8be4f6d04bd87220aa8f72eb0850edc4</id>
<content type='text'>
Update the config.h and defconfig files for the commands that 8e3c036
converted over to Kconfig

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: ls102xa: Fix order of CSU indexes in ns_access.h</title>
<updated>2016-04-06T17:26:21Z</updated>
<author>
<name>Vincent Siles</name>
<email>vincent.siles@provenrun.com</email>
</author>
<published>2016-03-29T07:41:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=96077896ee01d890d2758ce39aaf81af5f60dc59'/>
<id>urn:sha1:96077896ee01d890d2758ce39aaf81af5f60dc59</id>
<content type='text'>
This patch aims to fix the order of CSU slave index for the LS1021a
board.

Signed-off-by: Vincent Siles &lt;vincent.siles@provenrun.com&gt;
Reviewed-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
</feed>
