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<title>u-boot.git/arch/arm/include/asm/arch-mx5, branch v2011.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-mx5?h=v2011.09</id>
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<updated>2011-09-04T09:36:11Z</updated>
<entry>
<title>MX5: make use of GPIO framework for MX5 processor</title>
<updated>2011-09-04T09:36:11Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2011-08-21T08:51:06Z</published>
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<id>urn:sha1:7d8d0b1a4a7a679e4148a4e64d755321edc58f3e</id>
<content type='text'>
Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>ARM: MX51: PLL errata workaround</title>
<updated>2011-09-04T09:36:11Z</updated>
<author>
<name>David Jander</name>
<email>david@protonic.nl</email>
</author>
<published>2011-07-13T21:11:53Z</published>
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<id>urn:sha1:9db1bfa110ac411ab3468e817f7f74b2439eb8c8</id>
<content type='text'>
This is a port of the official PLL errata workaround from Freescale to
mainline u-boot.
The PLL's in the i.MX51 processor can go out of lock due to a metastable
condition in an analog flip-flop when used at high frequencies.
This workaround implements an undocumented feature in the PLL (dither
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.

Signed-off-by: David Jander &lt;david@protonic.nl&gt;
</content>
</entry>
<entry>
<title>MX5: Update to autogenerated asm-offsets.h</title>
<updated>2011-07-14T13:41:24Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2011-07-07T03:37:06Z</published>
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<id>urn:sha1:0edf8b5b2fa0d210ebc4d6da0fd1aceeb7e44e47</id>
<content type='text'>
On i.MX5, the asm-offsets.h file is not yet generated as it should be.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
CC: Matthias Weisser &lt;weisserm@arcor.de&gt;
</content>
</entry>
<entry>
<title>MX5: Introduce a function for setting the chip select size</title>
<updated>2011-07-04T08:55:26Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2011-06-07T07:02:52Z</published>
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<id>urn:sha1:a6e961c2923ec7a5351c16cd202d9376e44eaa3b</id>
<content type='text'>
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>MX5: Add iomux structure</title>
<updated>2011-07-04T08:55:26Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2011-06-07T07:02:51Z</published>
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<id>urn:sha1:a682b3f76bf441e7ccafa402b60ca30bc62751df</id>
<content type='text'>
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>MX5: Make the weim structure complete</title>
<updated>2011-07-04T08:55:26Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2011-06-07T07:02:50Z</published>
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<id>urn:sha1:ac4020e3c0337d449e0cd20ff7e9f0744a5f131b</id>
<content type='text'>
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>SPI: mxc_spi: replace fixed offsets with structures</title>
<updated>2011-02-01T23:54:43Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2011-01-19T22:46:33Z</published>
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<id>urn:sha1:ac87c17d344ede52d8d421addf92cbb2e271f73e</id>
<content type='text'>
This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>MX5: Add initial support for MX53 processor</title>
<updated>2011-02-01T23:54:41Z</updated>
<author>
<name>Liu Hui-R64343</name>
<email>r64343@freescale.com</email>
</author>
<published>2011-01-03T22:27:35Z</published>
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<id>urn:sha1:595f3e56459797d70e842bce93d0dd01455a329f</id>
<content type='text'>
Add initial support for Freescale MX53 processor,

- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro

Signed-off-by: Jason Liu  &lt;r64343@freescale.com&gt;
</content>
</entry>
<entry>
<title>imx: Get fec mac address from fuse</title>
<updated>2010-11-21T17:24:20Z</updated>
<author>
<name>Liu Hui-R64343</name>
<email>r64343@freescale.com</email>
</author>
<published>2010-11-18T23:45:55Z</published>
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<id>urn:sha1:565e39c57769a45a5eaed5e4c86357e817cf64e1</id>
<content type='text'>
The patch is to support getting FEC MAC address from fuse bank.

Signed-off-by: Jason Liu &lt;r64343@freescale.com&gt;
Tested-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>mx51evk: support new relocation scheme</title>
<updated>2010-10-28T09:43:23Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.gsc@gmail.com</email>
</author>
<published>2010-10-28T02:13:15Z</published>
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<id>urn:sha1:1ab027cbf6536f40348699a7b7bfa8bbedf88c8e</id>
<content type='text'>
This patch is to fix build breakage and support new relocation
scheme for mx51evk.

- Correct IRAM base address and add size definition

  The IRAM starts from 0x1FFE0000 on final revsion i.mx51 than
  0x1FFE8000 which is for older revision.

- Include imx-regs.h in mx51evk.h

  Definitions like CSD0_BASE_ADDR and IRAM_BASE_ADDR can be
  referred to.

- Define CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE

  They are used to define init RAM layout.

- Remove comment for CONFIG_SYS_GBL_DATA_SIZE which has been
  buried by Wolfgang's commit below

  25ddd1fb: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value

Signed-off-by: Shawn Guo &lt;shawn.gsc@gmail.com&gt;
</content>
</entry>
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