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<title>u-boot.git/arch/arm/include/asm/arch-mx5, branch v2012.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-mx5?h=v2012.07</id>
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<updated>2012-07-10T09:35:38Z</updated>
<entry>
<title>mx6: Allow mx6 to access the IPUv3 registers</title>
<updated>2012-07-10T09:35:38Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-31T07:23:55Z</published>
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<id>urn:sha1:05d4df1d8a955228968fe9e9382f335950670cdd</id>
<content type='text'>
Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>mx53: Allow IPUv3 driver to also work on mx53</title>
<updated>2012-05-25T08:36:29Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-15T08:01:16Z</published>
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<id>urn:sha1:fff6ef72b33050344362ca441cdb6b5f9b4fb8b0</id>
<content type='text'>
Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and
mx53 SoCs.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged</title>
<updated>2012-05-15T06:31:35Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2012-05-09T10:07:31Z</published>
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<id>urn:sha1:c4559daa9158367878ddb3e115d60d41e0322b1f</id>
<content type='text'>
After an update to the MX51 reference manual (Rev. 5), the
values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH
are now clearly wrong:

"Bit 13:
High / Low Output Voltage Range. This bit selects the output voltage mode for
SD2_CMD. 0 High output voltage mode
1 Low output voltage mode"

The values are currently negated in code - fixed.

Reported-by: David Jander &lt;david.jander@protonic.nl&gt;
Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
CC: Marek Vasut &lt;marek.vasut@gmail.com&gt;
CC: David Jander &lt;david.jander@protonic.nl&gt;
Acked-by: David Jander &lt;david.jander@protonic.nl&gt;
Acked-by: Marek Vasut &lt;marek.vasut@gmail.com&gt;
</content>
</entry>
<entry>
<title>mx53loco: Add CONFIG_REVISION_TAG</title>
<updated>2012-05-15T06:31:34Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-08T03:40:49Z</published>
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<id>urn:sha1:54cd1dee8f9537c2e3d5bfe2029bf31b2b1cf2f3</id>
<content type='text'>
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.

The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.

Suggested-by: Yu Li &lt;yk@magniel.com&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>mx53loco: Allow to print CPU information at a later stage</title>
<updated>2012-05-15T06:31:32Z</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2012-04-30T08:12:03Z</published>
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<id>urn:sha1:1fc56f1cb06a1d83bd90626677a236761e812324</id>
<content type='text'>
Print CPU information within board_late_init().

This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>mx5: Add clock config interface</title>
<updated>2012-05-15T06:31:32Z</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2012-04-30T08:12:02Z</published>
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<id>urn:sha1:70cc86a6307ab4de4a2cd1125e5b9c857242a4e3</id>
<content type='text'>
mx5: Add clock config interface

Add clock config interface support, so that we
can configure CPU or DDR clock in the later init

Signed-off-by: Jason Liu &lt;jason.hui@linaro.org&gt;
Signed-off-by: Eric Miao &lt;eric.miao@linaro.org&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>imx-common: Factor out get_ahb_clk()</title>
<updated>2012-05-15T06:31:32Z</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2012-04-29T08:11:13Z</published>
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<id>urn:sha1:6a376046ef3b2417cf9fbfbfad300fa6f026c816</id>
<content type='text'>
get_ahb_clk() is a common function between mx5 and mx6.

Place it into imx-common directory.

Cc: Dirk Behme &lt;dirk.behme@googlemail.com&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>MX53: add function to set SATA clock to internal</title>
<updated>2012-05-15T06:31:30Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2012-02-22T00:24:38Z</published>
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<id>urn:sha1:8c38b5d03d701134b7d6e4eeea94c229f7470d27</id>
<content type='text'>
The MX53 SATA interface can use an internal clock (USB PHY1)
instead of an external clock. This is an undocumented feature, but used
on most Freescale's evaluation boards, such as MX53-loco.

As stated by Freescale's support:

Fuses (but not pins) may be used to configure SATA clocks.
Particularly the i.MX53 Fuse_Map contains the next information
about configuring SATA clocks :
	SATA_ALT_REF_CLK[1:0] (offset 0x180C)

'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
CC: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>MX5: Add definitions for SATA controller</title>
<updated>2012-05-15T06:31:30Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2012-02-22T00:24:36Z</published>
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<id>urn:sha1:d87c85ce4314cab49bf2664bb094df748a90cb29</id>
<content type='text'>
Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
CC: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
CC: Dirk Behme &lt;dirk.behme@de.bosch.com&gt;
</content>
</entry>
<entry>
<title>Define UART4 and UART5 base addresses</title>
<updated>2012-05-15T06:31:30Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2012-02-22T00:24:33Z</published>
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<id>urn:sha1:4a9677e53f609d7f1043dde12b6c15c37baa579f</id>
<content type='text'>
Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
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