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<title>u-boot.git/arch/arm/include/asm/arch-mx6, branch v2016.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-mx6?h=v2016.01</id>
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<updated>2015-12-07T14:03:08Z</updated>
<entry>
<title>imx: mx6: fix reg base address when runtime usage</title>
<updated>2015-12-07T14:03:08Z</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-11-30T08:04:51Z</published>
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<id>urn:sha1:0c890879fe2a5731df7aee3dd38e455008fa9977</id>
<content type='text'>
Should use parenthese to wrap the macro definition, otherwise
we will encounter error like the following:

"
if (base_addr != LCDIF1_BASE_ADDR) {
    puts("Wrong LCD interface!\n");
    return -EINVAL;
}
"

Without this patch, we will always encounter "Wrong LCD interface".

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: mx6: add clock api for lcdif</title>
<updated>2015-11-12T16:40:53Z</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-10-29T07:54:47Z</published>
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<id>urn:sha1:ad153782e07ee3a95ccef6b6eeddaaaec918421f</id>
<content type='text'>
Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video.
The three API can be used to configure lcdif related clock when
CONFIG_VIDEO_MXS enabled.

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: mx6: crm_reg: add LCDIF related macros</title>
<updated>2015-11-12T16:40:52Z</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-10-29T07:54:46Z</published>
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<id>urn:sha1:64ffef05e0deac5a388836e16aa8496b59e5ed5f</id>
<content type='text'>
Add i.MX6UL/SX LCDIF related macros. Discard uneccessary
'#ifdef xxx'.

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: mx6: fix register address</title>
<updated>2015-11-12T16:40:52Z</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-10-29T07:54:45Z</published>
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<id>urn:sha1:b1ce1fb52792b1c2f620b63a206f6c7c2601ef4a</id>
<content type='text'>
1. Move WDOG3_BASE_ADDR to '#if !(defined(__ASSEMBLY__))'.
2. Add i.MX6UL LCDIF register base address. And Introduce
   LCDIF1_BASE_ADDR to support runtime check.
3. include &lt;asm/imx-common/regs-lcdif.h&gt; for imx-regs.h to avoid
   building error for mxsfb.c, since mxsfb.c use imx-regs.h.

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: hab: rework secure boot support for imx6</title>
<updated>2015-10-30T14:20:57Z</updated>
<author>
<name>Adrian Alonso</name>
<email>aalonso@freescale.com</email>
</author>
<published>2015-10-12T18:48:08Z</published>
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<id>urn:sha1:7a7281a91c2e0b27bc276ef879e896ed8669342a</id>
<content type='text'>
Rework secure boot support for imx6, move existing hab support
for imx6 into imx-common for SoC reuse.

Signed-off-by: Adrian Alonso &lt;aalonso@freescale.com&gt;
</content>
</entry>
<entry>
<title>imx: cpu: move common chip revision id's</title>
<updated>2015-10-30T14:20:56Z</updated>
<author>
<name>Adrian Alonso</name>
<email>aalonso@freescale.com</email>
</author>
<published>2015-10-12T18:48:07Z</published>
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<id>urn:sha1:fc5ad4778d91dabbeca3bc05a78cb669686f0a9c</id>
<content type='text'>
Move common chip revision id's to main cpu header file
mx25 generic include cpu header for chip revision

Signed-off-by: Adrian Alonso &lt;aalonso@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm, imx: add some gpr register defines</title>
<updated>2015-10-30T14:08:39Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2015-09-25T10:31:48Z</published>
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<id>urn:sha1:d62f2f8cdfd7ee9bd1e61fa1e71723340f870071</id>
<content type='text'>
add some missing gpr register defines.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
<entry>
<title>pci: pcie_imx: Fix hang on mx6qp</title>
<updated>2015-10-15T13:05:13Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2015-10-13T14:01:27Z</published>
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<id>urn:sha1:aaf87f03ad709ff9f00819ef1eb001e878ad0a54</id>
<content type='text'>
PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: imx: imx-common: init: move arch init common setup</title>
<updated>2015-09-13T08:11:53Z</updated>
<author>
<name>Adrian Alonso</name>
<email>aalonso@freescale.com</email>
</author>
<published>2015-09-02T18:54:15Z</published>
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<id>urn:sha1:50a082a88c54975eaa6b6ae39b50936802783387</id>
<content type='text'>
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.

Signed-off-by: Adrian Alonso &lt;aalonso@freescale.com&gt;
</content>
</entry>
<entry>
<title>mxc: ocotp fix hole in shadow registers</title>
<updated>2015-09-02T13:39:51Z</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-08-26T07:40:47Z</published>
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<id>urn:sha1:7296a023580f3cf1e386d6924b226bc1f4db2217</id>
<content type='text'>
There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.

Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.

When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
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