u-boot.git/arch/arm/include/asm/arch-mx6, branch v2016.09

mx6: ddr: Allow changing REFSEL and REFR fields

2016-09-06T16:22:48Z

Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam Reviewed-by: Eric Nelson

ARM: Move SYS_CACHELINE_SIZE over to Kconfig

2016-08-26T21:04:46Z

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud Cc: Marek Vasut Cc: Stefano Babic Cc: Prafulla Wadaskar Cc: Luka Perkov Cc: Stefan Roese Cc: Nagendra T S Cc: Vaibhav Hiremath Acked-by: Lokesh Vutla Cc: Steve Rae Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Stefan Agner Acked-by: Heiko Schocher Cc: Mateusz Kulikowski Cc: Peter Griffin Acked-by: Paul Kocialkowski Cc: Anatolij Gustschin Acked-by: "Pali Rohár" Cc: Adam Ford Cc: Steve Sakoman Cc: Grazvydas Ignotas Cc: Nishanth Menon Cc: Stephen Warren Cc: Robert Baldyga Cc: Minkyu Kang Cc: Thomas Weber Cc: Masahiro Yamada Cc: David Feng Cc: Alison Wang Cc: Michal Simek Cc: Simon Glass Cc: York Sun Cc: Shengzhou Liu Cc: Mingkai Hu Cc: Prabhakar Kushwaha Cc: Aneesh Bansal Cc: Saksham Jain Cc: Qianyu Gong Cc: Wang Dongsheng Cc: Alex Porosanu Cc: Hongbo Zhang Cc: tang yuantian Cc: Rajesh Bhagat Cc: Josh Wu Cc: Bo Shen Cc: Viresh Kumar Cc: Hannes Schmelzer Cc: Thomas Chou Cc: Joe Hershberger Cc: Sam Protsenko Cc: Bin Meng Cc: Christophe Ricard Cc: Anand Moon Cc: Beniamino Galvani Cc: Carlo Caione Cc: huang lin Cc: Sjoerd Simons Cc: Xu Ziyuan Cc: "jk.kernel@gmail.com" Cc: "Ariel D'Alessandro" Cc: Kever Yang Cc: Samuel Egli Cc: Chin Liang See Cc: Dinh Nguyen Cc: Hans de Goede Cc: Ian Campbell Cc: Siarhei Siamashka Cc: Boris Brezillon Cc: Andre Przywara Cc: Bernhard Nortmann Cc: Wolfgang Denk Cc: Ben Whitten Cc: Tom Warren Cc: Alexander Graf Cc: Sekhar Nori Cc: Vitaly Andrianov Cc: "Andrew F. Davis" Cc: Murali Karicheri Cc: Carlos Hernandez Cc: Ladislav Michl Cc: Ash Charles Cc: Mugunthan V N Cc: Daniel Allred Cc: Gong Qianyu Signed-off-by: Tom Rini Acked-by: Masahiro Yamada Acked-by: Chin Liang See Tested-by: Stephen Warren Acked-by: Paul Kocialkowski

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

2016-05-24T17:42:03Z

arch/arm: add SEC JR0 offset

2016-05-18T15:51:46Z

Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu Reviewed-by: York Sun

imx: mx6: mx6sl_pins: add GPIO variant for SD1_DAT5

2016-05-17T15:52:19Z

This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9. Signed-off-by: Eric Nelson Reviewed-by: Peng Fan

MX6UL: Add definition for UART6 base address

2016-04-19T14:36:54Z

Define the UART6_BASE_ADDR for MX6UL. Signed-off-by: Fabio Estevam

imx: mx6: Fix procedure to switch the parent of LDB_DI_CLK

2016-04-19T14:05:12Z

Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. This patch was ported from the 3.10.17 NXP kernel http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d NXP errata number: ERR009219, EB821 Signed-off-by: Akshay Bhat Cc: Stefano Babic Cc: Fabio Estevam

arm: mx6: Add UART8 base address for i.MX6UL

2016-03-26T13:16:12Z

Add the base address for the i.MX6UL so that this UART can be used. Signed-off-by: Stefan Roese Cc: Ye Li Cc: Fabio Estevam Cc: Stefano Babic

imx: mx6: implement functions to boot auxiliary core

2016-02-21T10:46:26Z

Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li Signed-off-by: Peng Fan

imx: mx6sx Add RDC mappings of masters and peripherals

2016-02-21T10:46:26Z

Add the definitions for the RDC mappings for i.MX6 SoloX. Signed-off-by: Ye.Li Signed-off-by: Peng Fan