u-boot.git/arch/arm/include/asm/arch-mx7, branch v2016.11

imx: mx7: Add plugin support

2016-10-24T08:57:16Z

Add mx7_plugin.S which calls boot rom setup function, generate the second ivt, and jump back to boot rom. Signed-off-by: Peng Fan Signed-off-by: Ye Li Cc: Stefano Babic Reviewed-by: Tom Rini

ARM: Move SYS_CACHELINE_SIZE over to Kconfig

2016-08-26T21:04:46Z

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud Cc: Marek Vasut Cc: Stefano Babic Cc: Prafulla Wadaskar Cc: Luka Perkov Cc: Stefan Roese Cc: Nagendra T S Cc: Vaibhav Hiremath Acked-by: Lokesh Vutla Cc: Steve Rae Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Stefan Agner Acked-by: Heiko Schocher Cc: Mateusz Kulikowski Cc: Peter Griffin Acked-by: Paul Kocialkowski Cc: Anatolij Gustschin Acked-by: "Pali Rohár" Cc: Adam Ford Cc: Steve Sakoman Cc: Grazvydas Ignotas Cc: Nishanth Menon Cc: Stephen Warren Cc: Robert Baldyga Cc: Minkyu Kang Cc: Thomas Weber Cc: Masahiro Yamada Cc: David Feng Cc: Alison Wang Cc: Michal Simek Cc: Simon Glass Cc: York Sun Cc: Shengzhou Liu Cc: Mingkai Hu Cc: Prabhakar Kushwaha Cc: Aneesh Bansal Cc: Saksham Jain Cc: Qianyu Gong Cc: Wang Dongsheng Cc: Alex Porosanu Cc: Hongbo Zhang Cc: tang yuantian Cc: Rajesh Bhagat Cc: Josh Wu Cc: Bo Shen Cc: Viresh Kumar Cc: Hannes Schmelzer Cc: Thomas Chou Cc: Joe Hershberger Cc: Sam Protsenko Cc: Bin Meng Cc: Christophe Ricard Cc: Anand Moon Cc: Beniamino Galvani Cc: Carlo Caione Cc: huang lin Cc: Sjoerd Simons Cc: Xu Ziyuan Cc: "jk.kernel@gmail.com" Cc: "Ariel D'Alessandro" Cc: Kever Yang Cc: Samuel Egli Cc: Chin Liang See Cc: Dinh Nguyen Cc: Hans de Goede Cc: Ian Campbell Cc: Siarhei Siamashka Cc: Boris Brezillon Cc: Andre Przywara Cc: Bernhard Nortmann Cc: Wolfgang Denk Cc: Ben Whitten Cc: Tom Warren Cc: Alexander Graf Cc: Sekhar Nori Cc: Vitaly Andrianov Cc: "Andrew F. Davis" Cc: Murali Karicheri Cc: Carlos Hernandez Cc: Ladislav Michl Cc: Ash Charles Cc: Mugunthan V N Cc: Daniel Allred Cc: Gong Qianyu Signed-off-by: Tom Rini Acked-by: Masahiro Yamada Acked-by: Chin Liang See Tested-by: Stephen Warren Acked-by: Paul Kocialkowski

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

2016-05-24T17:42:03Z

arch/arm: add SEC JR0 offset

2016-05-18T15:51:46Z

Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu Reviewed-by: York Sun

imx: iomux-v3: fix UART input selects

2016-05-17T15:52:20Z

Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2.

imx: mx7: implement functions to boot auxiliary core

2016-02-21T10:46:26Z

Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li Signed-off-by: Peng Fan

imx: mx7d: Add RDC support

2016-02-21T10:46:26Z

Add the peripherals/masters definitions and registers base addresses for mx7d RDC. Signed-off-by: Ye.Li Signed-off-by: Peng Fan

imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7

2016-02-21T10:20:54Z

Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by: Ulises Cardenas Reviewed-by: Stefano Babic

imx: mx7: default enable MDIO open drain

2016-01-24T11:15:14Z

The management data input/output (MDIO) requires open-drain, i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports this feature. So to TO1.1, need to enable open drain by setting bits GPR0[8:7] for TO1.1. Signed-off-by: Peng Fan Cc: Stefano Babic

imx: lcdif: use one register structure for i.MXes

2015-11-12T16:38:09Z

Share one lcdif structure for i.MXes. 1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7 2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-common Signed-off-by: Peng Fan Cc: Stefano Babic