u-boot.git/arch/arm/include/asm/arch-mx7ulp, branch v2020.04Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-mx7ulp?h=v2020.042020-01-16T20:02:56Zmx7ulp: Move SoC base address to a common file2020-01-16T20:02:56ZFabio Estevamfestevam@gmail.com2019-10-23T14:08:55Zurn:sha1:9c27310ac23ce1966f9629d73973c458412a0085
SoC base addresses should better go into a common SoC file instead
of repeating the definition in each board file.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
mx7ulp: scg: Remove unnused scg_a7_apll_init()2019-12-06T11:05:08ZFabio Estevamfestevam@gmail.com2019-11-05T12:47:53Zurn:sha1:d136eb9bfeca97131aaa6daf214018823e8a3869
scg_a7_apll_init() is not called anywhere, so remove such dead code
Signed-off-by: Fabio Estevam <festevam@gmail.com>
i.MX7ULP: Set A7 core frequency to 500Mhz for B0 chip2019-10-08T14:35:16ZYe Liye.li@nxp.com2019-07-22T01:25:08Zurn:sha1:df3572e93033d7620767ed6dc9790dceb110636c
The normal target frequency for ULP A7 core is 500Mhz, but now ROM
set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX7ULP: Fix wrong i2c configuration name2019-10-08T14:35:16ZYe Liye.li@nxp.com2019-07-22T01:24:53Zurn:sha1:61bf6173cd65f8c937c40759c923ba52ca03374b
Wrong I2c driver configuration name is used in codes, so I2c driver is
not built. Correct it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX7ULP: Fix PCC register bits mask and offset issue2019-10-08T14:35:16ZYe Liye.li@nxp.com2019-07-22T01:24:47Zurn:sha1:a0f4f7ee606296ac1090bd358696ee822b67d8cc
The offset for FRAC and the mask for PCD are not correct.
If we set FRAC, we can't get the right frequency. Fix them
to correct value.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX7ULP: Fix system reset after a7 rtc alarm expired.2019-10-08T14:35:16ZBai Pingping.bai@nxp.com2019-07-22T01:24:42Zurn:sha1:7777406a8a023bdfe18d106138c61eeaa15dd5b4
The board will reboot if A7 core enter mem mode by rtc, then M4 core
enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
to fix this issue.
Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access
it. So check the CPU rev and not apply the settings for B0.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx: i.MX7ULP: add get_boot_device2019-10-08T14:35:16ZPeng Fanpeng.fan@nxp.com2019-07-22T01:24:37Zurn:sha1:e92fca66a3966c54d86977539fabe57596b62d76
Add get_boot_device for i.MX7ULP
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
imx: define ARCH_MXC for i.MX8/8M/7ULP2019-06-11T08:43:00ZPeng Fanpeng.fan@nxp.com2019-05-09T08:33:55Zurn:sha1:16529ff255a37df29133ebffc62e59793cbf6d86
Without this definition, fsl_esdhc will access reserved registers
on i.MX chips, so define ARCH_MXC to fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
mx7ulp: Add common plugin codes for mx7ulp2019-06-11T08:42:48ZYe Liye.li@nxp.com2019-05-16T03:18:51Zurn:sha1:15bae9a86d16b1e35a71bb745e5b91d8de0dfd34
Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2
header.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx_lpi2c: Update lpi2c driver to support imx82018-07-12T09:08:41ZYe Liye.li@nxp.com2018-07-08T03:46:40Zurn:sha1:9b2ebcc06048cf49c2f8a8d152177ed1a8363878
Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory
to u-boot include directory as a common header file.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>