u-boot.git/arch/arm/include/asm/arch-mx7ulp, branch v2022.07

WS cleanup: remove SPACE(s) followed by TAB

2021-09-30T13:08:16Z

Signed-off-by: Wolfgang Denk

arm: imx: sys_proto: move boot mode define to common header

2021-08-09T12:46:50Z

These defines could be reused by i.MX8ULP, so move them to common header. Signed-off-by: Peng Fan

caam: enable support for iMX7ULP

2021-04-08T07:18:29Z

Signed-off-by: Franck LENORMAND Signed-off-by: Peng Fan

arm: Don't include common.h in header files

2020-05-18T18:54:24Z

It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass

mx7ulp: Move SoC base address to a common file

2020-01-16T20:02:56Z

SoC base addresses should better go into a common SoC file instead of repeating the definition in each board file. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan

mx7ulp: scg: Remove unnused scg_a7_apll_init()

2019-12-06T11:05:08Z

scg_a7_apll_init() is not called anywhere, so remove such dead code Signed-off-by: Fabio Estevam

i.MX7ULP: Set A7 core frequency to 500Mhz for B0 chip

2019-10-08T14:35:16Z

The normal target frequency for ULP A7 core is 500Mhz, but now ROM set the core frequency to 413Mhz. So change it to 500Mhz in u-boot. Signed-off-by: Ye Li Signed-off-by: Peng Fan

i.MX7ULP: Fix wrong i2c configuration name

2019-10-08T14:35:16Z

Wrong I2c driver configuration name is used in codes, so I2c driver is not built. Correct it. Signed-off-by: Ye Li Signed-off-by: Peng Fan

i.MX7ULP: Fix PCC register bits mask and offset issue

2019-10-08T14:35:16Z

The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value. Signed-off-by: Ye Li Signed-off-by: Peng Fan

i.MX7ULP: Fix system reset after a7 rtc alarm expired.

2019-10-08T14:35:16Z

The board will reboot if A7 core enter mem mode by rtc, then M4 core enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode to fix this issue. Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access it. So check the CPU rev and not apply the settings for B0. Signed-off-by: Bai Ping Signed-off-by: Peng Fan