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<title>u-boot.git/arch/arm/include/asm/arch-rockchip, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-rockchip?h=v2016.09</id>
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<updated>2016-08-05T23:56:07Z</updated>
<entry>
<title>rk3399: add basic soc driver</title>
<updated>2016-08-05T23:56:07Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2016-07-29T02:35:25Z</published>
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<id>urn:sha1:b0b3c86521e0fe4cca3676adfc0b937d77456f9e</id>
<content type='text'>
This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: Add a way to obtain the main clock device</title>
<updated>2016-07-26T02:46:45Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-17T21:23:16Z</published>
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<id>urn:sha1:a617c5d3e2c22355ee9abc455bbb0b36e124a00a</id>
<content type='text'>
On Rockchip SoCs we typically have a main clock device that uses the Soc
clock driver. There is also a fixed clock for the oscillator. Add a function
to obtain the core clock.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>cosmetic: rockchip: rk3288: rename rkclk_configure_cpu</title>
<updated>2016-07-26T02:44:20Z</updated>
<author>
<name>Heiko Stübner</name>
<email>heiko@sntech.de</email>
</author>
<published>2016-07-15T22:17:16Z</published>
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<id>urn:sha1:b339b5dbca4c776a4c138b852082fad2df826410</id>
<content type='text'>
The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: sdram: Move all DT decoding to ofdata_to_platdata()</title>
<updated>2016-07-15T02:40:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-04T17:58:34Z</published>
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<id>urn:sha1:fb4baf5d58c212f0b78ac125ee2d7c595b6437e9</id>
<content type='text'>
It is more correct to avoid touching the device tree in the probe() method.
Update the driver to work this way. Note that only SPL needs to fiddle with
the SDRAM registers, so decoding the platform data fully is not necessary in
U-Boot proper.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: Update the sdram-channel property to support of-platdata</title>
<updated>2016-07-15T02:40:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-04T17:58:25Z</published>
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<id>urn:sha1:9ca7e6720e96e82be1de9ec0ba6bac9f1beeb02f</id>
<content type='text'>
Add an extra byte so that this data is not byteswapped. Add a comment to
the code to explain the purpose.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: convert API to match reset/mailbox style</title>
<updated>2016-06-19T23:05:55Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-06-17T15:44:00Z</published>
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<id>urn:sha1:135aa95002646c46e89de93fa36adad1b010548f</id>
<content type='text'>
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3</title>
<updated>2016-05-27T15:00:48Z</updated>
<author>
<name>Sjoerd Simons</name>
<email>sjoerd.simons@collabora.co.uk</email>
</author>
<published>2016-02-28T21:25:00Z</published>
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<id>urn:sha1:2f3920047ae7d70fef7bb9a0c7c5c0eee677d9f7</id>
<content type='text'>
Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various
GMAC related fields.

Signed-off-by: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: rk3288: Add clock support for the gmac ethernet interface</title>
<updated>2016-05-27T15:00:48Z</updated>
<author>
<name>Sjoerd Simons</name>
<email>sjoerd.simons@collabora.co.uk</email>
</author>
<published>2016-02-28T21:24:59Z</published>
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<id>urn:sha1:0aefc0b0c7eba963c88eca893a546f3e786615ac</id>
<content type='text'>
Setup the clocks for the gmac ethernet interface. This assumes the mac
clock is fed by an external clock which is common on RK3288 based
devices.

Signed-off-by: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: video: Add LVDS support in vop driver</title>
<updated>2016-03-14T21:24:10Z</updated>
<author>
<name>Jacob Chen</name>
<email>jacob-chen@iotwrt.com</email>
</author>
<published>2016-03-14T03:20:18Z</published>
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<id>urn:sha1:8530783594f6de14ec6d4b7bf804437d6e1a4f5f</id>
<content type='text'>
LVDS have a different display out mode, add code to get right flag.

The vop_ip decide display device and the remote_vop_id decide which
vop was being used. So we should use the remote_vop_id to set DCLK_VOP.

Signed-off-by: Jacob Chen &lt;jacob-chen@iotwrt.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: video: Add a display driver for rockchip LVDS</title>
<updated>2016-03-14T21:06:33Z</updated>
<author>
<name>Jacob Chen</name>
<email>jacob-chen@iotwrt.com</email>
</author>
<published>2016-03-14T03:20:16Z</published>
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<id>urn:sha1:35ac89dd8fe7e9373d8c4336e7fbe93ae3fd59d7</id>
<content type='text'>
Some Rockchip SoCs support LVDS output. Add a display driver for this so
that these displays can be used on supported boards.

Signed-off-by: Jacob Chen &lt;jacob-chen@iotwrt.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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