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<title>u-boot.git/arch/arm/include/asm/arch-socfpga, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-socfpga?h=main</id>
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<updated>2015-05-07T03:21:15Z</updated>
<entry>
<title>ARM: socfpga: move SoC headers to mach-socfpga/include/mach</title>
<updated>2015-05-07T03:21:15Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-04-21T11:38:22Z</published>
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<id>urn:sha1:30088b09975017c90979d55bc0ead58ca424652f</id>
<content type='text'>
Move headers to mach-socfpga as well.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: spl: Add stub sdram.h</title>
<updated>2015-04-21T10:37:12Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-04-21T10:30:09Z</published>
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<id>urn:sha1:b284d268aff2253b162c636bc63d8fd289159296</id>
<content type='text'>
Since the SoCFPGA SDRAM support is not yet applied to u-boot, we still
need to be able to compile the codebase. Introduce stub functions which
temporarily supplement the missing SDRAM setup functions.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;clsee@opensource.altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Pavel Machek &lt;pavel@denx.de&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Cc: Vince Bridgers &lt;vbridger@opensource.altera.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: spl: allow bootrom to enable IOs after warm reset</title>
<updated>2015-04-21T10:23:16Z</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@opensource.altera.com</email>
</author>
<published>2015-03-30T22:01:07Z</published>
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<id>urn:sha1:08e463ee8a7a5641e191be2a8e934d8284d1ca55</id>
<content type='text'>
Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: add functions to bring sdram, timer, and uart out of reset</title>
<updated>2015-04-21T10:23:16Z</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@opensource.altera.com</email>
</author>
<published>2015-03-30T22:01:04Z</published>
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<id>urn:sha1:c218f85ea18d57beecc36a3460f08e929d81fcd6</id>
<content type='text'>
These functions will be needed for use by the SPL for enabling the
console and sdram initialization.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
</content>
</entry>
<entry>
<title>socfpga: correctly increment freeze_controller_base address</title>
<updated>2014-12-06T12:53:57Z</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@opensource.altera.com</email>
</author>
<published>2014-11-26T18:14:33Z</published>
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<id>urn:sha1:b9b5cf0ea3c5c141f31cc0c4c8edebbfd9ff5866</id>
<content type='text'>
Correctly increment the base address of the freeze controller. And since
SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Vince Bridgers &lt;vbridger@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>socfpga: add missing struct member fifo_triple_byte</title>
<updated>2014-12-06T12:53:57Z</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@opensource.altera.com</email>
</author>
<published>2014-11-26T18:14:32Z</published>
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<id>urn:sha1:5d2f930de0e5222957e103c8eb5df2b7238dd4b4</id>
<content type='text'>
socfpga_scan_manager structure was missing a data member.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Vince Bridgers &lt;vbridger@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.h</title>
<updated>2014-12-06T12:52:47Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2014-11-16T11:47:00Z</published>
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<id>urn:sha1:481549f8c1fa3a40729d0ff15c25380a043b6d41</id>
<content type='text'>
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Vince Bridgers &lt;vbridger@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Add socfpga_spim_enable() to reset_manager.c</title>
<updated>2014-11-07T15:09:10Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2014-11-07T12:50:30Z</published>
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<id>urn:sha1:a877bec3ecd7961211a59b2c130e055e0f771976</id>
<content type='text'>
This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI
driver is enabled.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Vince Bridgers &lt;vbridger@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Pavel Machek &lt;pavel@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target</title>
<updated>2014-11-07T14:58:31Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2014-11-07T13:10:41Z</published>
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<id>urn:sha1:51c580c6c92c01884f520f4ffaeb6885ee8e666e</id>
<content type='text'>
This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.

Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.

One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.

Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Vince Bridgers &lt;vbridger@altera.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Pavel Machek &lt;pavel@denx.de&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Zap spl.h and ad-hoc related syms</title>
<updated>2014-10-27T01:26:24Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2014-10-16T10:25:40Z</published>
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<id>urn:sha1:34584d190db5cfc879dea71ba345d15fe8bf348b</id>
<content type='text'>
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Vince Bridgers &lt;vbridger@altera.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
</content>
</entry>
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