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<title>u-boot.git/arch/arm/include/asm/arch-spear, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2015-09-11T21:15:14Z</updated>
<entry>
<title>arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4</title>
<updated>2015-09-11T21:15:14Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2015-09-02T09:10:58Z</published>
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<id>urn:sha1:da53ba0219c65c11a673ec11c0c2ad371c74251f</id>
<content type='text'>
This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
switch between both ECC schemes for backwards compatibility.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm: spear: Move to common SPL infrastructure</title>
<updated>2015-08-28T16:33:16Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2015-08-18T07:27:17Z</published>
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<id>urn:sha1:2fbdbda1c7c48aa622812054633afc6cdff91eab</id>
<content type='text'>
The SPL implementation for SPEAr600 is older than the common SPL
infrastructure. This patch now moves the SPEAr600 SPL over to the
common SPL code.

Tested on the only SPEAr board that currently uses SPL in mainline
U-Boot, the x600.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Vipin Kumar &lt;vk.vipin@gmail.com&gt;
</content>
</entry>
<entry>
<title>usb: spear: Add support for both SPEAr600 EHCI controllers</title>
<updated>2015-08-19T20:30:20Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2015-08-18T07:27:18Z</published>
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<id>urn:sha1:e8d056989a7302eda4e3ed263a375fd175a4e15f</id>
<content type='text'>
USB EHCI on SPEAr600 has not been tested for a while. The base controller
addresses are missing. This patch adds the defines to the header. And adds
the missing code.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Vipin Kumar &lt;vk.vipin@gmail.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>spear: move CONFIG_SYS_I2C_BASE from arch-spear/hardware to board configs</title>
<updated>2014-02-20T05:49:02Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>Alexey.Brodkin@synopsys.com</email>
</author>
<published>2014-02-10T08:20:11Z</published>
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<id>urn:sha1:f93f589ca2defd02fa76a3d0cde695d61820390d</id>
<content type='text'>
Having CONFIG_SYS_I2C_BASE requires DW I2C driver to explicitly include
&lt;arch/hardware.h&gt; which other platforms may not have at all.

It's always good to have a driver platform-independent.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;

Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Vipin Kumar &lt;vipin.kumar@st.com&gt;
Cc: Armando Visconti &lt;armando.visconti@st.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>SPL: ARM: spear: Add SPL support for SPEAr600 platform</title>
<updated>2012-07-07T12:07:43Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2012-01-03T15:49:01Z</published>
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<id>urn:sha1:4ae8bc4392ec038566276e15c4dfe29f0fe9682f</id>
<content type='text'>
This patch adds SPL support for SPEAr600. Currently only SNOR
(Serial NOR) flash support is included. Other boot devices
(NAND, MMC, USB ...) may be added with later patches.

Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Amit Virdi &lt;amit.virdi@st.com&gt;
Cc: Vipin Kumar &lt;vipin.kumar@st.com&gt;
</content>
</entry>
<entry>
<title>GPIO: Add SPEAr GPIO driver</title>
<updated>2012-07-07T12:07:42Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2012-02-14T13:01:36Z</published>
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<id>urn:sha1:2cb06a4fda4e7a88c734adaec9eeb5059e50f76b</id>
<content type='text'>
Tested on x600 (SPEAr600).

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>cleanup/SPEAr: Remove unnecessary parenthesis</title>
<updated>2012-07-07T12:07:42Z</updated>
<author>
<name>Amit Virdi</name>
<email>amit.virdi@st.com</email>
</author>
<published>2012-05-07T07:37:01Z</published>
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<id>urn:sha1:bc0bdf4c2296d02802ddfa76f349cbba3a869138</id>
<content type='text'>
In SPEAr configuration files, unnecessary paranthesis are used in some
\#defines. Remove them as they serve no purpose

Signed-off-by: Amit Virdi &lt;amit.virdi@st.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>SPEAr: Correct SoC ID offset in misc configuration space</title>
<updated>2012-07-07T12:07:42Z</updated>
<author>
<name>Shiraz Hashim</name>
<email>shiraz.hashim@st.com</email>
</author>
<published>2012-05-07T07:37:00Z</published>
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<id>urn:sha1:f28e5c946d6c88b1c8639896863c7ad7d8889bf4</id>
<content type='text'>
SoC Core ID offset is 0x30 in miscellaneous configuration address
space. It was wrongly mentioned as periph2 clk enable.

Signed-off-by: Shiraz Hashim &lt;shiraz.hashim@st.com&gt;
Signed-off-by: Amit Virdi &lt;amit.virdi@st.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>SPEAr: explicitly select clk src for UART</title>
<updated>2012-07-07T12:07:42Z</updated>
<author>
<name>Shiraz Hashim</name>
<email>shiraz.hashim@st.com</email>
</author>
<published>2012-05-07T07:36:59Z</published>
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<id>urn:sha1:7c885a0e5532abcd6bc802d21a7858420e5c127b</id>
<content type='text'>
UART in u-boot intends to run on 48MHz clock supplied by USB PLL.
Explicitly select the intended clock source.

Signed-off-by: Shiraz Hashim &lt;shiraz.hashim@st.com&gt;
Signed-off-by: Amit Virdi &lt;amit.virdi@st.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
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