u-boot.git/arch/arm/include/asm/arch-tegra124, branch v2016.01

ARM: tegra124: Clear IDDQ when enabling PLLC

2015-09-16T23:11:31Z

Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet Signed-off-by: Thierry Reding Signed-off-by: Tom Warren

ARM: tegra: Implement clk_m

2015-09-16T23:10:22Z

On currently supported SoCs, clk_m always runs at the same frequency as the oscillator input. However newer SoC generations such as Tegra210 no longer have that restriction. Prepare for that by separating clk_m from the oscillator clock and allow SoC code to override the clk_m rate. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren

tegra: Add missing tegra124 peripherals

2015-06-09T16:56:14Z

There are some missing entries in the tables. Add them. Signed-off-by: Simon Glass Signed-off-by: Tom Warren

tegra: Introduce SRAM repair on tegra124

2015-06-09T16:56:14Z

This is required in order to avoid instability when running from caches after the kernel starts. Signed-off-by: Simon Glass Signed-off-by: Tom Warren

ARM: tegra: Enable SMMU when going non-secure

2015-05-13T16:24:16Z

Make sure to enable the SMMU when booting the kernel in non-secure mode. This is necessary because some of the SMMU registers are restricted to TrustZone-secured requestors, hence the kernel wouldn't be able to turn the SMMU on. At the same time, enable translation for all memory clients for the same reasons. The kernel will still be able to control SMMU IOVA translation using the per-SWGROUP enable bits. Signed-off-by: Thierry Reding Signed-off-by: Jan Kiszka Signed-off-by: Tom Warren

tegra124: Add PSCI support for Tegra124

2015-05-13T16:24:15Z

This is based on Thierry Reding's work and uses Ian Campell's preparatory patches. It comes with full support for CPU_ON/OFF PSCI services. The algorithm used in this version for turning CPUs on and off was proposed by Peter De Schrijver and Thierry Reding in http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It consists of first enabling CPU1..3 via the PMC, just to powergate them again with the help of the Flow Controller. Once the Flow Controller is in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF PSCI requests. Signed-off-by: Jan Kiszka Signed-off-by: Tom Warren

tegra124: Add more registers to struct mc_ctlr

2015-05-13T16:24:14Z

I will need mc_security_cfg0/1 in a future patch and I added the rest while debugging, so thought I might as well commit them. Signed-off-by: Ian Campbell Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini Reviewed-by: Thierry Reding Tested-by: Thierry Reding Tested-by: Ian Campbell Signed-off-by: Tom Warren

tegra: video: support eDP displays on Tegra124 devices

2015-05-13T16:24:11Z

Connect up the clocks and the eDP driver to make these displays work with Tegra124-based devices. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Tom Warren

tegra124: clock: Add display clocks and functions

2015-05-13T16:24:09Z

Add functions to provide access to the display clocks on Tegra124 including setting the clock rate for an EDP display. Signed-off-by: Simon Glass Signed-off-by: Tom Warren

tegra: Move the pwm into tegra-common

2015-05-13T16:24:06Z

This is needed for tegra124 also, so make it common and add a header file for tegra124. Signed-off-by: Simon Glass Signed-off-by: Tom Warren