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<title>u-boot.git/arch/arm/include/asm/arch-tegra2/tegra2.h, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-tegra2/tegra2.h?h=master</id>
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<updated>2012-09-01T12:58:21Z</updated>
<entry>
<title>tegra20: rename tegra2 -&gt; tegra20</title>
<updated>2012-09-01T12:58:21Z</updated>
<author>
<name>Allen Martin</name>
<email>amartin@nvidia.com</email>
</author>
<published>2012-08-31T08:30:00Z</published>
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<id>urn:sha1:00a2749d7be5b0e6cb6435187ec8fea600b44627</id>
<content type='text'>
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin &lt;amartin@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: usb: Fix device enumeration problem of USB1</title>
<updated>2012-07-09T20:44:34Z</updated>
<author>
<name>Jim Lin</name>
<email>jilin@nvidia.com</email>
</author>
<published>2012-06-24T20:40:57Z</published>
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<id>urn:sha1:8b3f7bf7ec95816a7d2f89331e8877a351b3ec7c</id>
<content type='text'>
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.

Therefore we clear that bit after Port Reset in order to proceed
later device enumeration.

Signed-off-by: Jim Lin &lt;jilin@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm: Tegra: Use ODMDATA from BCT in IRAM</title>
<updated>2012-07-07T12:07:21Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2012-05-30T21:06:09Z</published>
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<id>urn:sha1:76e350b7a3c568c8d27cf72f98036ec3ddb64f31</id>
<content type='text'>
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.

Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
</content>
</entry>
<entry>
<title>tegra: Add tegra_get_chip_type() to detect SKU</title>
<updated>2012-05-15T06:31:37Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2012-04-02T13:18:50Z</published>
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<id>urn:sha1:d515362d4d6f83be818f71d37a4600041a520ab5</id>
<content type='text'>
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: Add flow, gp_padctl, fuse, sdram headers</title>
<updated>2012-05-15T06:31:37Z</updated>
<author>
<name>Yen Lin</name>
<email>yelin@nvidia.com</email>
</author>
<published>2012-04-02T13:18:49Z</published>
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<id>urn:sha1:f6f767a4040110b400726e9859ea51a7ade10474</id>
<content type='text'>
These headers provide access to additional Tegra features.

flow - start/stop CPUs
sdram - parameters for SDRAM
fuse - access to on-chip fuses / security settings
gp_padctl - pad control and general purpose registers

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Yen Lin &lt;yelin@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE</title>
<updated>2012-03-29T06:12:49Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2012-02-03T15:13:52Z</published>
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<id>urn:sha1:f4589a7d6f477876c18eb8087e3ee7fa0a8655ca</id>
<content type='text'>
Change this name to fit with the current convention in the Tegra
header file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: usb: Add support for Tegra USB peripheral</title>
<updated>2012-03-29T06:12:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2012-02-27T10:52:49Z</published>
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<id>urn:sha1:87f938c9f7372f587a43fe7babcb171ee0a0672f</id>
<content type='text'>
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.

Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:

        aliases {
		/* This defines the order of our USB ports */
                usb0 = "/usb@0xc5008000";
                usb1 = "/usb@0xc5000000";
        };

drivers/usb/host files ONLY: Acked-by: Remy Bohmer &lt;linux@bohmer.net&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra2: spi: Add SPI driver for Tegra2 SOC</title>
<updated>2011-12-24T09:23:30Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren.nvidia@gmail.com</email>
</author>
<published>2011-11-05T09:48:11Z</published>
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<id>urn:sha1:9112ef8d89e3e496ba6f73276f17dd5c2b93877f</id>
<content type='text'>
This driver supports SPI on Tegra2, running at 48MHz.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Acked-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
</content>
</entry>
<entry>
<title>arm: Tegra2: GPIO: Add basic GPIO definitions</title>
<updated>2011-04-27T17:38:10Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren.nvidia@gmail.com</email>
</author>
<published>2011-04-14T12:09:40Z</published>
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<id>urn:sha1:c5e93131fadfc69f733929873c1f80a822778a13</id>
<content type='text'>
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm: Tegra2: add support for A9 CPU init</title>
<updated>2011-04-27T17:38:09Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren.nvidia@gmail.com</email>
</author>
<published>2011-04-14T12:18:06Z</published>
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<id>urn:sha1:74652cf684fc8678a3c5377b1532394e2025ea49</id>
<content type='text'>
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
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