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<title>u-boot.git/arch/arm/include/asm/arch-tegra20, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-tegra20?h=v2016.09</id>
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<updated>2016-05-31T16:53:56Z</updated>
<entry>
<title>ARM: tegra: use DT bindings for GPIO naming</title>
<updated>2016-05-31T16:53:56Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-05-12T18:07:39Z</published>
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<id>urn:sha1:01a97a11db75c1a006da7b40d8ba4a325f05960c</id>
<content type='text'>
There are currently many places that define the list of all Tegra GPIOs;
the DT binding header and custom Tegra-specific header file gpio.h. Fix
the redundancy by replacing everything with the DT binding header file.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: video: Move LCD enums into the driver</title>
<updated>2016-02-16T16:17:53Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-30T23:37:58Z</published>
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<id>urn:sha1:bfda03770cc9a05be89d03e90c275e88f12e4174</id>
<content type='text'>
There is no need to have these in a separate file as they are not
referenced from anywhere else.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: video: Convert tegra20 LCD driver to driver model</title>
<updated>2016-02-16T16:17:52Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-30T23:37:56Z</published>
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<id>urn:sha1:9e6866d3b6687aaab854b29dad9809c7569e61a0</id>
<content type='text'>
Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.

Boards which use this are fixed up, but only seaboard is tested.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: video: Merge the two config structures together</title>
<updated>2016-02-16T16:17:52Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-30T23:37:55Z</published>
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<id>urn:sha1:ce0c474a72a72efe83808473a3411986a564e86b</id>
<content type='text'>
We have a structure for the display panel and another for the controller.
There is some overlap between them. Merge them to simplify the driver.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: video: Merge the display driver into one file</title>
<updated>2016-02-16T16:17:52Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-30T23:37:53Z</published>
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<id>urn:sha1:71cafc3fba4d91722375b0ea2213c494f36356d4</id>
<content type='text'>
At present we have code in arch/arm and code in drivers/video. Move it all
into drivers/video since it is a display driver and our current approach is
to put all driver code in drivers/.

Make a few functions static now that they are not used outside the file.
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Implement clk_m</title>
<updated>2015-09-16T23:10:22Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-08-20T09:42:19Z</published>
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<id>urn:sha1:c043c0259cd88f39cdca5f98af8b10f178660745</id>
<content type='text'>
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: Move display controller header into common</title>
<updated>2015-05-13T16:24:10Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-04-15T03:03:35Z</published>
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<id>urn:sha1:2eb70de6b1a340fbad28ac36d34adb8e6c809c5c</id>
<content type='text'>
Allow this to be used by other Tegra SoCs.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: Move the pwm into tegra-common</title>
<updated>2015-05-13T16:24:06Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-04-15T03:03:22Z</published>
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<id>urn:sha1:1c82c2f60a6f5a5c16f1ea7144da479e78760e06</id>
<content type='text'>
This is needed for tegra124 also, so make it common and add a header file
for tegra124.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: ARM720t: remove empty asm/arch/hardware.h</title>
<updated>2015-04-23T12:52:27Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-04-21T12:59:35Z</published>
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<id>urn:sha1:526fcc220360fa6acceaa06d5c3c5bb2de57b2f0</id>
<content type='text'>
arch/arm/cpu/arm720t/start.S includes &lt;asm/arch/hardware.h&gt;,
but the hardware.h headers of ARM720T boards are all empty.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: Stephen Warren &lt;swarren@nvidia.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: pinmux: account for different drivegroup base registers</title>
<updated>2015-03-04T17:09:01Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2015-02-24T21:08:29Z</published>
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<id>urn:sha1:790f7719e2635a3ff3f44473b060e01b5b5ebf74</id>
<content type='text'>
Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
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