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<title>u-boot.git/arch/arm/include/asm/arch-tegra30, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/arch-tegra30?h=v2016.09</id>
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<updated>2016-05-31T16:53:56Z</updated>
<entry>
<title>ARM: tegra: use DT bindings for GPIO naming</title>
<updated>2016-05-31T16:53:56Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-05-12T18:07:39Z</published>
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<id>urn:sha1:01a97a11db75c1a006da7b40d8ba4a325f05960c</id>
<content type='text'>
There are currently many places that define the list of all Tegra GPIOs;
the DT binding header and custom Tegra-specific header file gpio.h. Fix
the redundancy by replacing everything with the DT binding header file.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Add more SPDX-License-Identifier tags</title>
<updated>2016-01-19T13:31:21Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-01-15T03:05:13Z</published>
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<id>urn:sha1:5b8031ccb4ed6e84457d883198d77efc307085dc</id>
<content type='text'>
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Implement clk_m</title>
<updated>2015-09-16T23:10:22Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-08-20T09:42:19Z</published>
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<id>urn:sha1:c043c0259cd88f39cdca5f98af8b10f178660745</id>
<content type='text'>
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: ARM720t: remove empty asm/arch/hardware.h</title>
<updated>2015-04-23T12:52:27Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-04-21T12:59:35Z</published>
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<id>urn:sha1:526fcc220360fa6acceaa06d5c3c5bb2de57b2f0</id>
<content type='text'>
arch/arm/cpu/arm720t/start.S includes &lt;asm/arch/hardware.h&gt;,
but the hardware.h headers of ARM720T boards are all empty.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: Stephen Warren &lt;swarren@nvidia.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: pinmux: account for different drivegroup base registers</title>
<updated>2015-03-04T17:09:01Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2015-02-24T21:08:29Z</published>
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<id>urn:sha1:790f7719e2635a3ff3f44473b060e01b5b5ebf74</id>
<content type='text'>
Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: pinmux: handle feature removal on newer SoCs</title>
<updated>2015-03-04T17:08:59Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2015-02-24T21:08:25Z</published>
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<id>urn:sha1:439f57684e9fff3209f966365a18c328f858c623</id>
<content type='text'>
On some future SoCs, some of the per-drive-group features no longer
exist. Add some ifdefs to support this.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: pinmux: simplify some defines</title>
<updated>2015-03-04T17:08:59Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2015-02-24T21:08:24Z</published>
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<id>urn:sha1:7a28441f4d89cac6885a7e817e41379c83cb35aa</id>
<content type='text'>
Future SoCs have a slightly different combination of pinmux options per
pin. This will be simpler to handle if we simply have one define per
option, rather than grouping various options together, in combinations
that don't align with future chips.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Implement powergate support</title>
<updated>2014-12-18T20:19:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:08Z</published>
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<id>urn:sha1:48510c089b18482de36210ec3f70d8908e8daf90</id>
<content type='text'>
Implement the powergate API that allows various power partitions to be
power up and down.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Implement tegra_plle_enable()</title>
<updated>2014-12-18T20:19:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:06Z</published>
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<id>urn:sha1:a7230745504552095594362b81caaa33b5d7da5e</id>
<content type='text'>
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Use mem size from MC in combination with get_ram_size()</title>
<updated>2014-10-22T16:30:55Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel@ziswiler.com</email>
</author>
<published>2014-10-10T21:32:32Z</published>
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<id>urn:sha1:8c33ba7b1d85ea98d39171523858bbd7cd44f166</id>
<content type='text'>
On popular request this now completes the Warren's work started for
TK1:

aeb3fcb35956461077804720b8a252d50758d7e0
ARM: tegra: Use mem size from MC rather than ODMDATA

In addition to the move of using the Tegra memory controller (MC)
register rather than ODMDATA for T20, T30 and T114 as well it further
uses the generic get_ram_size() function (see "common/memsize.c")
&lt;supposed to be used in each and every U-Boot port&gt;TM. Added benefit is
that it should &lt;catch 99% of hardware related (i. e. reliably
reproducible) memory errors&gt; as well.

Thoroughly tested on the various Toradex line of Tegra modules
available which unfortunately does not include T114 and T124 (yet at
least) plus on the Jetson TK1.

Based-on-work-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Based-on-work-by: Tom Warren &lt;twarren@nvidia.com&gt;
Signed-off-by: Marcel Ziswiler &lt;marcel@ziswiler.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
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