u-boot.git/arch/arm/include/asm/armv7.h, branch master

ARM: bootm: Add support for starting Linux through OPTEE-OS on ARMv7a

2025-11-06T17:26:18+00:00

Add support for jumping to Linux kernel through OPTEE-OS on ARMv7a.
This is only supported if U-Boot runs in PL1 secure. This change adds
two components, one is fitImage OPTEE-OS loadable handler, which makes
a note of OPTEE-OS being loaded and stores the load address for later
jump to it. The second part is the actual jump to Linux through OPTEE-OS.
The jump through OPTEE-OS requires set up of multiple CPU registers, r1
and r2 are passed through, r0 and r3 have to be set to 0, lr is set to
Linux kernel entry point. This setup is done by new assembler function
boot_jump_linux_via_optee().

The boot_jump_linux_via_optee() also includes STM32MP13xx late TZC
configuration write, this cannot be moved easily, hence the ifdef.

Signed-off-by: Marek Vasut

ARM: armv7: Add C wrapper for allow_unaligned()

2023-07-01T15:29:15+00:00

Rename current assembler implementation of allow_unaligned() to
v7_arch_cp15_allow_unaligned() and add it into armv7.h header,
then add C wrapper of allow_unaligned().

This fixes misbehavior when linking U-Boot on ARMv7a i.MX6Q, where the
CPU specific allow_unaligned() implementation was ignored and instead the
__weak allow_unaligned() implementation from lib/efi_loader/efi_setup.c
was used, which led to "data abort" just before booting Linux via tftp,
in efi_dp_from_file() -> path_to_uefi() -> utf16_put() .

The problem is triggerd by c7c0ca37673 ("efi_loader: fix efi_dp_from_file()") .
Adding the wrapper fixes the problem.

Fixes: 78f90aaeecc ("arm: armv7: allow unaligned memory access")
Signed-off-by: Marek Vasut

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12+00:00

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini

armv7: Move L2CTLR read/write to common

2017-09-30T22:33:33+00:00

L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.

Cc: Tom Warren 
Signed-off-by: Jagan Teki 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich

ARM: Add an empty secure stack section

2016-07-15T13:54:57+00:00

Until now we've been using memory beyond psci_text_end as stack space
for the secure monitor or PSCI implementation, even if space was not
allocated for it.

This was partially fixed in ("ARM: allocate extra space for PSCI stack
in secure section during link phase"). However, calculating stack space
from psci_text_end in one place, while allocating the space in another
is error prone.

This patch adds a separate empty secure stack section, with space for
CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also
__secure_stack_start and __secure_stack_end symbols. The linker script
handles calculating the correct VMAs for the stack section. For
platforms that relocate/copy the secure monitor before using it, the
space is not allocated in the executable, saving space.

For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page
of stack space for 4 CPUs is allocated, matching the previous behavior.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Hans de Goede

arm/arm64: Move barrier instructions into separate header

2016-05-12T15:13:03+00:00

Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes , which does not compile on arm64.

Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.

This fixes compilation for 64-bit sunxi boards (Pine64).

Acked-by: Ian Campbell 
Signed-off-by: Andre Przywara

virt-dt: Allow reservation of secure region when in a RAM carveout

2015-05-13T16:24:14+00:00

In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.

Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons

This will be used in a subsequent patch for Jetson-TK1.

Signed-off-by: Jan Kiszka 
Signed-off-by: Tom Warren

ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions

2015-05-13T16:24:13+00:00

CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC: Tang Yuantian 
CC: York Sun 
CC: Steve Rae 
CC: Andre Przywara 
Signed-off-by: Jan Kiszka 
Tested-by: Alison Wang 
Signed-off-by: Tom Warren

ARM: cpu: Add ARMv7 barrier operations support

2015-04-16T11:53:26+00:00

This enables ARMv7 barrier operations support when
march=armv7-a is enabled.

Using CP15 barriers causes U-Boot bootm command crash when
transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU.
Using ARMv7 barrier operations instead of the deprecated CP15 barriers
helps to avoid these issues.

Signed-off-by: Valentine Barshak 
Signed-off-by: Vladimir Barinov 
Reviewed-by: Tom Rini 
Reviewed-by: Nobuhiro Iwamatsu

ARM: Introduce erratum workaround for 454179

2015-03-13T13:28:48+00:00

454179: Stale prediction may inhibit target address misprediction on
	next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon 
Tested-by: Matt Porter 
Reviewed-by: Tom Rini