u-boot.git/arch/arm/include/asm/armv8, branch master

armv8: mmu: add a function to help debug TLB lookups

2026-06-17T15:55:00Z

Implement a super basic software TLB walk which can look up a single address in the TLB and print each stage of the translation. This is helpful for debugging TLB issues and will be compiled out if unused. Example output on QEMU aarch64: Performing software TLB lookup of address 0x50100000 va_bits: 40 PTE: 0x47fe0000. addr[47:39]: 0x000 (offset 0x00000) L0: 0x47fe0000 -> TABLE (0x47fe1000) PTE: 0x47fe1000. addr[38:30]: 0x001 (offset 0x00008) L1: 0x47fe1008 -> BLOCK (0x40000000) [0x40000000 - 0x80000000] Reviewed-by: Ilias Apalodimas Signed-off-by: Casey Connolly

arm: armv8: mmu: move mmu enablement out of mmu_setup

2026-05-25T15:29:50Z

Currently mmu_setup for ARMv8 performs two functions, first it sets up the page tables based the memory map provided by the board and then it enables the MMU. However for some platforms runtime fixes to the generated page tables are required before the MMU can be enabled, such as K3 family of SoCs. Therefore this patch moves the enablement of the MMU out of mmu_setup and to a standalone mmu_enable function to give more granular control to the platforms. Note that no functional changes are intended from this patch. Reviewed-by: Ilias Apalodimas Signed-off-by: Anshul Dalal

arm: armv8: mmu: add mmu_unmap_reserved_mem

2025-10-22T18:05:52Z

For armv8, U-Boot uses a static map defined as 'mem_map' for configuring the MMU's page tables, done by mmu_setup. Though this works well for simpler platforms, it makes creating runtime carveouts by modifying the static array at runtime exceedingly complex like in mach-snapdragon/board.c. Creation of such carveouts are much better handled by APIs such as mmu_change_region_attr once the page tables are configured. Usually such carveouts are configured via the device-tree's reserved-memory node which provides the address and size for the carveout. Therefore this patch adds mmu_unmap_reserved_mem which acts as a wrapper over mmu_change_region_attr, helping unmap a reserved-memory region. Reviewed-by: Ilias Apalodimas Signed-off-by: Anshul Dalal Tested-by: Wadim Egorov

arm: armv8: mmu: add mem_map_from_dram_banks

2025-10-22T18:05:52Z

For armv8, U-Boot uses a static map defined as 'mem_map' for configuring the MMU as part of mmu_setup. But since the exact configuration of memory banks might not be known at build time, many platforms such as imx9, versal2 etc. utilize gd->bd->bi_dram to configure the static map at runtime. Therefore this patch adds a new API mem_map_from_dram_banks that modifies the static map in a similar way. Allowing the caller to map all dram banks by just passing the index to last entry in their mem_map and it's length. Reviewed-by: Dhruva Gole Signed-off-by: Anshul Dalal Tested-by: Wadim Egorov

arm: armv8: mmu: export mmu_setup

2025-10-22T18:05:52Z

The mmu_setup function configures the page tables based on the board supplied mem_map struct array. It is called implicitly as part of dcache_enable but this limits us to only be able to use APIs such as mmu_change_region_attr only after caches are enabled. This might lead to speculative accesses before we can unmap a region that is marked as cacheable in the static memory map. Therefore this patch exports the mmu_setup function in mmu.h allowing users to have more control over when the mmu is configured. For K3 specifically this allows for the following configuration sequence as part of enable_caches: static mem_map fixups (TODO) -> mmu_setup -> carveouts using mmu_change_region_attr (TODO) -> icache/dcache enable Reviewed-by: Dhruva Gole Reviewed-by: Ilias Apalodimas Signed-off-by: Anshul Dalal Tested-by: Wadim Egorov

arm64: Add MIDR entry for Cortex-A720

2025-09-26T22:47:48Z

Add MIDR entry for Cortex-A720 core. Signed-off-by: Marek Vasut

arm64: Add MIDR entries for Cortex-A55, A73 and A75

2025-04-03T02:02:27Z

Add MIDR entries for Cortex-A55, Cortex-A73 and Cortex-A75 cores and update the is_coretex_a entries. Signed-off-by: Peter Robinson

meminfo: add memory details for armv8

2025-03-14T11:30:12Z

Upcoming patches are mapping memory with RO, RW^X etc permsissions. Fix the meminfo command to display them properly Acked-by: Jerome Forissier Reviewed-by: Caleb Connolly Signed-off-by: Ilias Apalodimas

arm64: Add MIDR entries for Cortex-A57 and Cortex-A76

2025-01-12T22:49:58Z

Add MIDR entries for Cortex-A57 and Cortex-A76 cores. Those are used on R-Car Gen3 and Gen4 SoCs respectively. Reviewed-by: Paul Barker Reviewed-by: Peter Robinson Signed-off-by: Marek Vasut

arm64: Convert core type check macros into inline functions

2025-01-12T22:49:58Z

Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent. Reviewed-by: Paul Barker Reviewed-by: Peter Robinson Signed-off-by: Marek Vasut