u-boot.git/arch/arm/include/asm/armv8, branch v2015.10

armv8/mmu: Set bits marked RES1 in TCR

2015-10-15T12:46:43Z

For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding

armv8/mmu: Clean up TCR programming

2015-10-15T12:41:20Z

Use the inner shareable attribute for memory, which makes more sense considering that this code is called when caches are being enabled. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding

armv8: fsl-lsch3: Rewrite MMU translation table entries

2015-09-02T02:49:27Z

This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang Signed-off-by: York Sun

armv8: Fix TCR macros for shareability attribute

2015-07-20T18:44:40Z

For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register. Signed-off-by: Zhichun Hua Signed-off-by: York Sun

armv8/fsl-lsch3: Change normal memory shareability

2015-02-24T21:08:22Z

According to hardware implementation, a single outer shareable global coherence group is defined. Inner shareable has not bee enabled. Signed-off-by: York Sun

ARMv8: Adjust MMU setup

2014-07-03T06:40:48Z

Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun CC: David Feng

arm64: core support

2014-01-09T15:08:44Z

Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood Signed-off-by: David Feng