u-boot.git/arch/arm/include/asm/armv8, branch v2016.01Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/armv8?h=v2016.012015-11-30T17:11:11Zarmv8/layerscape: Update MMU table with execute-never bits2015-11-30T17:11:11ZAlison Wangb18965@freescale.com2015-11-05T03:15:49Zurn:sha1:d764129d30768df72cd07844dd50d11e74b0de14
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
armv8/fsl_lsch2: Add fsl_lsch2 SoC2015-10-29T17:34:00ZMingkai HuMingkai.Hu@freescale.com2015-10-26T11:47:51Zurn:sha1:8281c58fd46d095e28e60b2fb0ce84b4444896f8
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
armv8/mmu: Set bits marked RES1 in TCR2015-10-15T12:46:43ZThierry Redingtreding@nvidia.com2015-08-20T09:52:14Zurn:sha1:ad3d6e88a1a4e6aacc55b39c2bad1528100784c0
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
armv8/mmu: Clean up TCR programming2015-10-15T12:41:20ZThierry Redingtreding@nvidia.com2015-08-20T09:52:13Zurn:sha1:55aa0bed9803b8a5bd3e462fd712741c2e1cff1b
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
armv8: fsl-lsch3: Rewrite MMU translation table entries2015-09-02T02:49:27ZAlison Wangb18965@freescale.com2015-08-18T03:22:05Zurn:sha1:997992201541dcec67cf1ed568e442efd57cbac4
This patch rewrites MMU translation table entries. To start, all table
entries are written as "invalid", then "device-ngnrnr" and "normal" are
written to the entries to enable access to specific addresses.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
armv8: Fix TCR macros for shareability attribute2015-07-20T18:44:40ZZhichun Huazhichun.hua@freescale.com2015-06-29T07:49:37Zurn:sha1:21a257b9b3b29ddb1445fdafe12e05727080a198
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
armv8/fsl-lsch3: Change normal memory shareability2015-02-24T21:08:22ZYork Sunyorksun@freescale.com2015-01-06T21:11:22Zurn:sha1:6c747f4ad4eef87152f8d6de2169efe0a6a7a57f
According to hardware implementation, a single outer shareable global
coherence group is defined. Inner shareable has not bee enabled.
Signed-off-by: York Sun <yorksun@freescale.com>
ARMv8: Adjust MMU setup2014-07-03T06:40:48ZYork Sunyorksun@freescale.com2014-06-23T22:15:53Zurn:sha1:22932ffc03e521130cfd33cae1fc2531eb42604a
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
arm64: core support2014-01-09T15:08:44ZDavid Fengfenghua@phytium.com.cn2013-12-14T03:47:35Zurn:sha1:0ae7653128c80a4f2920cbe9b124792c2fd9d9e0
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>