u-boot.git/arch/arm/include/asm/armv8, branch v2016.07

arm64: Remove non-full-va map code

2016-03-15T19:13:10Z

By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf

thunderx: Move mmu table into board file

2016-03-15T19:13:02Z

The MMU range table can vary depending on things we may only find out at runtime. While the very simple ThunderX variant does not change, other boards will, so move the definition from a static entry in a header file to the board file. Signed-off-by: Alexander Graf

arm64: Make full va map code more dynamic

2016-03-15T19:13:01Z

The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf

arm64: Disable TTBR1 maps in EL1

2016-03-15T19:13:00Z

When running in EL1, AArch64 knows two page table maps. One with addresses that start with all zeros (TTBR0) and one with addresses that start with all ones (TTBR1). In U-Boot we don't care about the high up maps, so just disable them to ensure we don't walk an invalid page table by accident. Reported-by: Mark Rutland Signed-off-by: Alexander Graf

thunderx: Calculate TCR dynamically

2016-03-15T19:12:59Z

Based on the memory map we can determine a lot of hard coded fields of TCR, like the maximum VA and max PA we want to support. Calculate those dynamically to reduce the chance for pit falls. Signed-off-by: Alexander Graf

armv8: New MMU setup code allowing to use 48+ bits PA/VA

2016-01-19T22:25:36Z

This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla

armv8/layerscape: Update MMU table with execute-never bits

2015-11-30T17:11:11Z

For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun Signed-off-by: Alison Wang Reported-by: Zhichun Hua

armv8/fsl_lsch2: Add fsl_lsch2 SoC

2015-10-29T17:34:00Z

Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang Signed-off-by: Hou Zhiqiang Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun

armv8/mmu: Set bits marked RES1 in TCR

2015-10-15T12:46:43Z

For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding

armv8/mmu: Clean up TCR programming

2015-10-15T12:41:20Z

Use the inner shareable attribute for memory, which makes more sense considering that this code is called when caches are being enabled. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding