<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/include/asm/armv8, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/armv8?h=v2016.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/armv8?h=v2016.09'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-07-19T18:33:53Z</updated>
<entry>
<title>ARMv8/layerscape: Add FSL PPA support</title>
<updated>2016-07-19T18:33:53Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2016-06-28T12:18:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f1dd4cadd20c3b6b2454b7f293265caa66f27fee'/>
<id>urn:sha1:f1dd4cadd20c3b6b2454b7f293265caa66f27fee</id>
<content type='text'>
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.

Use the secure firmware framework to integrate FSL PPA into U-Boot.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>ARMv8: add the secure monitor firmware framework</title>
<updated>2016-07-19T18:33:03Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2016-06-28T12:18:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b45db3b59035735a0479d8df260d2349cdc3c21c'/>
<id>urn:sha1:b45db3b59035735a0479d8df260d2349cdc3c21c</id>
<content type='text'>
This framework is introduced for ARMv8 secure monitor mode firmware.
The main functions of the framework are, on EL3, verify the firmware,
load it to the secure memory and jump into it, and while it returned
to U-Boot, do some necessary setups at the 'target exception level'
that is determined by the respective secure firmware.

So far, the framework support only FIT format image, and need to define
the name of which config node should be used in 'configurations' and
the name of property for the raw secure firmware image in that config.
The FIT image should be stored in Byte accessing memory, such as NOR
Flash, or else it should be copied to main memory to use this framework.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: mmu: Add support of non-identical mapping</title>
<updated>2016-07-15T16:01:43Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-06-24T23:46:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cd4b0c5feaaa524b44889cde8f58d4b121df8fed'/>
<id>urn:sha1:cd4b0c5feaaa524b44889cde8f58d4b121df8fed</id>
<content type='text'>
Introduce virtual and physical addresses in the mapping table. This change
have no impact on existing boards because they all use idential mapping.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: mmu: house cleaning</title>
<updated>2016-07-15T16:01:43Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-06-24T23:46:20Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=252cdb46ee33ff876823d0ce0a0190c3878c76ff'/>
<id>urn:sha1:252cdb46ee33ff876823d0ce0a0190c3878c76ff</id>
<content type='text'>
Make setup_pgtages() and get_tcr() available for platform code to
customize MMU tables.
Remove unintentional call of create_table().

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm64: Remove non-full-va map code</title>
<updated>2016-03-15T19:13:10Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2016-03-04T00:09:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7985cdf74b280f86a1c7440298a84f1fb2876fd9'/>
<id>urn:sha1:7985cdf74b280f86a1c7440298a84f1fb2876fd9</id>
<content type='text'>
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>thunderx: Move mmu table into board file</title>
<updated>2016-03-15T19:13:02Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2016-03-04T00:09:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d473f0c621513d3f1c42888c113b68f65b7e81cf'/>
<id>urn:sha1:d473f0c621513d3f1c42888c113b68f65b7e81cf</id>
<content type='text'>
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>arm64: Make full va map code more dynamic</title>
<updated>2016-03-15T19:13:01Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2016-03-04T00:09:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5e2ec773bb6c5acf22d8652112856e87cff86ea4'/>
<id>urn:sha1:5e2ec773bb6c5acf22d8652112856e87cff86ea4</id>
<content type='text'>
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>arm64: Disable TTBR1 maps in EL1</title>
<updated>2016-03-15T19:13:00Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2016-03-04T00:09:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9bb367a590feac21d674e4d2cee77702d4774819'/>
<id>urn:sha1:9bb367a590feac21d674e4d2cee77702d4774819</id>
<content type='text'>
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.

Reported-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>thunderx: Calculate TCR dynamically</title>
<updated>2016-03-15T19:12:59Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2016-03-04T00:09:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0691484ac1efb1981dfd1b38df9646128bafff32'/>
<id>urn:sha1:0691484ac1efb1981dfd1b38df9646128bafff32</id>
<content type='text'>
Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>armv8: New MMU setup code allowing to use 48+ bits PA/VA</title>
<updated>2016-01-19T22:25:36Z</updated>
<author>
<name>Sergey Temerkhanov</name>
<email>s.temerkhanov@gmail.com</email>
</author>
<published>2015-10-14T16:55:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=94f7ff36e521674a02145a3ff04b659c40122ba3'/>
<id>urn:sha1:94f7ff36e521674a02145a3ff04b659c40122ba3</id>
<content type='text'>
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov &lt;s.temerkhanov@gmail.com&gt;
Signed-off-by: Radha Mohan Chintakuntla &lt;rchintakuntla@cavium.com&gt;
</content>
</entry>
</feed>
