u-boot.git/arch/arm/include/asm/emif.h, branch master

arm: include: Remove duplicate newlines

2024-07-15T18:12:16+00:00

Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut

global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

2022-12-05T21:06:07+00:00

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini 
Reviewed-by: Simon Glass

arm: Don't include common.h in header files

2020-05-18T18:54:24+00:00

It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.

Update some header files in arch/arm to drop this.

Signed-off-by: Simon Glass

cmd: ti: Generalize cmd_ddr3 command

2018-01-19T20:49:26+00:00

Keystone and DRA7 based TI platforms uses same
EMIF memory controller. cmd_ddr3 command is customized
for keystone platforms, make it generic so that it can
be re used for DRA7  platforms.

Signed-off-by: Lokesh Vutla

arm: emif-common: Add suppport for enabling ECC

2018-01-19T20:49:25+00:00

For data integrity, the EMIF1 supports ECC on the data
written or read from the SDRAM. Add support for enabling
ECC support in EMIF1.

Signed-off-by: Lokesh Vutla 
Signed-off-by: Krunal Bhargav

arm: emif-common: Add ecc specific emif registers

2018-01-19T20:49:25+00:00

This is a slight difference in emif_ddr_phy_status register offsets for
DRA7xx EMIF and older versions. And ecc registers are available only
in DRA7xx EMIC. Add support for this difference and ecc registers.

Signed-off-by: Lokesh Vutla

arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm

2016-12-09T20:00:03+00:00

Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.

Signed-off-by: Jyri Sarha 
Reviewed-by: Tom Rini

ARM: DRA7: DDR: Enable SR in Power Management Control

2016-03-16T01:30:19+00:00

If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.

Signed-off-by: Nishanth Menon 
Signed-off-by: Lokesh Vutla 
Tested-by: Tom Rini 
Reviewed-by: Tom Rini

ARM: DRA7: emif: Enable interleaving for higher address space

2016-03-14T23:18:47+00:00

Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.

Signed-off-by: Lokesh Vutla 
Reviewed-by: Tom Rini

ARM: DRA7: emif: Check for enable bits before updating leveling output

2016-03-14T23:18:47+00:00

Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.

Signed-off-by: Lokesh Vutla 
Reviewed-by: Tom Rini