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<title>u-boot.git/arch/arm/include/asm/global_data.h, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>armv8: Add tlb_allocated to arch global data</title>
<updated>2016-07-15T16:01:43+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-06-24T23:46:19+00:00</published>
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<content type='text'>
When secure ram is used, MMU tables have to be put into secure ram.
To use common MMU code, gd-&gt;arch.tlb_addr will be used to host TLB
entry pointer. To save allocated memory for later use, tlb_allocated
variable is added to global data structure.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
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<pre>
When secure ram is used, MMU tables have to be put into secure ram.
To use common MMU code, gd-&gt;arch.tlb_addr will be used to host TLB
entry pointer. To save allocated memory for later use, tlb_allocated
variable is added to global data structure.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>armv8: Move secure_ram variable out of generic global data</title>
<updated>2016-07-15T16:01:43+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-06-24T23:46:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e61a7534e33063a76e105d895e5c6317f2d0cd76'/>
<id>e61a7534e33063a76e105d895e5c6317f2d0cd76</id>
<content type='text'>
Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
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<pre>
Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: Remove non-full-va map code</title>
<updated>2016-03-15T19:13:10+00:00</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2016-03-04T00:09:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7985cdf74b280f86a1c7440298a84f1fb2876fd9'/>
<id>7985cdf74b280f86a1c7440298a84f1fb2876fd9</id>
<content type='text'>
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
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<pre>
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: Make full va map code more dynamic</title>
<updated>2016-03-15T19:13:01+00:00</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2016-03-04T00:09:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5e2ec773bb6c5acf22d8652112856e87cff86ea4'/>
<id>5e2ec773bb6c5acf22d8652112856e87cff86ea4</id>
<content type='text'>
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
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<pre>
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: New MMU setup code allowing to use 48+ bits PA/VA</title>
<updated>2016-01-19T22:25:36+00:00</updated>
<author>
<name>Sergey Temerkhanov</name>
<email>s.temerkhanov@gmail.com</email>
</author>
<published>2015-10-14T16:55:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=94f7ff36e521674a02145a3ff04b659c40122ba3'/>
<id>94f7ff36e521674a02145a3ff04b659c40122ba3</id>
<content type='text'>
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov &lt;s.temerkhanov@gmail.com&gt;
Signed-off-by: Radha Mohan Chintakuntla &lt;rchintakuntla@cavium.com&gt;
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<pre>
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov &lt;s.temerkhanov@gmail.com&gt;
Signed-off-by: Radha Mohan Chintakuntla &lt;rchintakuntla@cavium.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: LS2080A: Rename LS2085A to reflect LS2080A</title>
<updated>2015-11-30T16:53:04+00:00</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar@freescale.com</email>
</author>
<published>2015-11-09T11:12:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=449372148f6d9b5b8bded88ed8eee5c581a4bf81'/>
<id>449372148f6d9b5b8bded88ed8eee5c581a4bf81</id>
<content type='text'>
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava &lt;pratiyush.srivastava@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava &lt;pratiyush.srivastava@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>omap-common: Common boot code OMAP3 support and cleanup</title>
<updated>2015-07-27T19:02:03+00:00</updated>
<author>
<name>Paul Kocialkowski</name>
<email>contact@paulk.fr</email>
</author>
<published>2015-07-15T14:02:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=60c7c30aa084588ef974663be3d22a1de7f66cbb'/>
<id>60c7c30aa084588ef974663be3d22a1de7f66cbb</id>
<content type='text'>
This introduces OMAP3 support for the common omap boot code, as well as a
major cleanup of the common omap boot code.

First, the omap_boot_parameters structure becomes platform-specific, since its
definition differs a bit across omap platforms. The offsets are removed as well
since it is U-Boot's coding style to use structures for mapping such kind of
data (in the sense that it is similar to registers). It is correct to assume
that romcode structure encoding is the same as U-Boot, given the description
of these structures in the TRMs.

The original address provided by the bootrom is passed to the U-Boot binary
instead of a duplicate of the structure stored in global data. This allows to
have only the relevant (boot device and mode) information stored in global data.
It is also expected that the address where the bootrom stores that information
is not overridden by the U-Boot SPL or U-Boot.

The save_omap_boot_params is expected to handle all special cases where the data
provided by the bootrom cannot be used as-is, so that spl_boot_device and
spl_boot_mode only return the data from global data.

All of this is only relevant when the U-Boot SPL is used. In cases it is not,
save_boot_params should fallback to its weak (or board-specific) definition.
save_omap_boot_params should not be called in that context either.

Signed-off-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</content>
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<pre>
This introduces OMAP3 support for the common omap boot code, as well as a
major cleanup of the common omap boot code.

First, the omap_boot_parameters structure becomes platform-specific, since its
definition differs a bit across omap platforms. The offsets are removed as well
since it is U-Boot's coding style to use structures for mapping such kind of
data (in the sense that it is similar to registers). It is correct to assume
that romcode structure encoding is the same as U-Boot, given the description
of these structures in the TRMs.

The original address provided by the bootrom is passed to the U-Boot binary
instead of a duplicate of the structure stored in global data. This allows to
have only the relevant (boot device and mode) information stored in global data.
It is also expected that the address where the bootrom stores that information
is not overridden by the U-Boot SPL or U-Boot.

The save_omap_boot_params is expected to handle all special cases where the data
provided by the bootrom cannot be used as-is, so that spl_boot_device and
spl_boot_mode only return the data from global data.

All of this is only relevant when the U-Boot SPL is used. In cases it is not,
save_boot_params should fallback to its weak (or board-specific) definition.
save_omap_boot_params should not be called in that context either.

Signed-off-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8/fsl-lsch3: Add support for second DDR clock</title>
<updated>2015-02-24T21:09:14+00:00</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2015-01-06T21:18:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b87e6f88e9218da3de371bb6cc8a34924153178e'/>
<id>b87e6f88e9218da3de371bb6cc8a34924153178e</id>
<content type='text'>
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>qe: add u-qe support to arm board</title>
<updated>2014-11-19T20:55:45+00:00</updated>
<author>
<name>Zhao Qiang</name>
<email>B45475@freescale.com</email>
</author>
<published>2014-09-25T05:52:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=93d3320417b16f331d5edb87409cd7a347c4eeaa'/>
<id>93d3320417b16f331d5edb87409cd7a347c4eeaa</id>
<content type='text'>
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.

Signed-off-by: Zhao Qiang &lt;B45475@freescale.com&gt;
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.

Signed-off-by: Zhao Qiang &lt;B45475@freescale.com&gt;
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: make gd a function for clang</title>
<updated>2014-09-09T11:51:08+00:00</updated>
<author>
<name>Jeroen Hofstee</name>
<email>jeroen@myspectrum.nl</email>
</author>
<published>2014-07-30T19:54:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c65a2abb6c0a9ab1c70f5241716066c9480ce96a'/>
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<content type='text'>
"clang does not support global register variables; this is
unlikely to be implemented soon because it requires additional
LLVM backend support" [1]

Workaround it by obtaining the value of gd/r9 by an inline
asm routine. Note there is no set routine added for ARM at the
moment, since most if not all updates of gd from c are actually
not needed for ARM.

[1] http://clang.llvm.org/docs/UsersManual.html

cc: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
Signed-off-by: Jeroen Hofstee &lt;jeroen@myspectrum.nl&gt;
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<pre>
"clang does not support global register variables; this is
unlikely to be implemented soon because it requires additional
LLVM backend support" [1]

Workaround it by obtaining the value of gd/r9 by an inline
asm routine. Note there is no set routine added for ARM at the
moment, since most if not all updates of gd from c are actually
not needed for ARM.

[1] http://clang.llvm.org/docs/UsersManual.html

cc: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
Signed-off-by: Jeroen Hofstee &lt;jeroen@myspectrum.nl&gt;
</pre>
</div>
</content>
</entry>
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