u-boot.git/arch/arm/include/asm/imx-common, branch v2014.10

vf610twr: Tune DDR initialization settings

2014-10-07T11:08:31Z

Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner

i2c: imx: add macros to setup pads for multiple SoC types

2014-09-09T13:32:32Z

Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types. Cc: Stefano Babic Cc: Tim Harvey Acked-by: Tim Harvey Signed-off-by: Nikita Kiryanov

arm: vf610: add NFC pin mux

2014-08-30T11:46:39Z

Add pin mux for NAND Flash Controller (NFC). NAND can be connected using 8 or 16 data lines, this patch adds pin mux entries for all 16 data lines. Signed-off-by: Stefan Agner

Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

2014-06-30T21:00:34Z

arm: imx: Add two macros for VF610 in IOMUX_PAD structure

2014-06-09T07:18:12Z

Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in IOMUX_PAD structure. Signed-off-by: Alison Wang

imx: iomux: add macros to setup iomux for multiple SoC types

2014-06-06T08:07:26Z

Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list and add macros for declaring the pad_list that take into account the SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL iomux). Cc: Stefan Roese Cc: Otavio Salvador Cc: Andy Ng Cc: Eric Nelson Cc: Tapani Utriainen Cc: Tom Rini Signed-off-by: Tim Harvey

iomux-v3: Add support for mx6sl LVE bit

2014-05-09T13:10:53Z

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad. LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused. Add support for it. Signed-off-by: Fabio Estevam Tested-by: Otavio Salvador

imx-common/video: add detect_hdmi

2014-04-15T10:23:57Z

this function is used by several board together with board_video_skip to detect if hdmi is plugged is order to select the display to use. So move it in imx-common to share it. Signed-off-by: Eric Bénard

imx-common: add board_video_skip

2014-04-15T10:23:56Z

this function is shared by several boards and thus can be factorized Signed-off-by: Eric Bénard Acked-by: Eric Nelson Acked-by: Stefano Babic

imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro

2014-01-03T14:44:05Z

The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau , Fabio Estevam and Eric Bénard for helping to properly trace this down. Signed-off-by: Otavio Salvador Acked-by: Stefano Babic