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<title>u-boot.git/arch/arm/include/asm/imx-common, branch v2015.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2015-06-08T06:41:54Z</updated>
<entry>
<title>dm: gpio: vf610: Add GPIO driver support</title>
<updated>2015-06-08T06:41:54Z</updated>
<author>
<name>Bhuvanchandra DV</name>
<email>bhuvanchandra.dv@toradex.com</email>
</author>
<published>2015-06-01T13:07:16Z</published>
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<id>urn:sha1:d348a943e77ed72dd809cecf03365552545382b2</id>
<content type='text'>
Add GPIO driver support to Freescale VF610

Signed-off-by: Bhuvanchandra DV &lt;bhuvanchandra.dv@toradex.com&gt;
</content>
</entry>
<entry>
<title>imx: dma: correct MXS_DMA_ALIGNMENT</title>
<updated>2015-05-26T12:14:49Z</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-05-20T02:28:48Z</published>
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<id>urn:sha1:ab87fc6bbd80f4e702e7dde102b1c74f0f4678b3</id>
<content type='text'>
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND:  ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>i2c: mxc: refactor i2c driver and support dm</title>
<updated>2015-05-15T00:49:36Z</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-05-14T23:29:12Z</published>
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<id>urn:sha1:71204e95ce13228a0c742cce137c3238f64581d8</id>
<content type='text'>
1. Introduce a new structure `struct mxc_i2c_bus`, this structure will
   used for non-DM and DM.
2. Remove `struct mxc_i2c_regs` structure, but use register offset to access
   registers based on `base` entry of `struct mxc_i2c_bus`.
3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform
   flags. A new flag is introduced, I2C_QUIRK_FLAG.
4. Most functions use `struct mxc_i2c_bus` as one of the parameters.
   Make most functions common to DM and non-DM, try to avoid duplicated code.
5. Support DM, but pinctrl is not included. Pinmux setting is still set
   by setup_i2c, but we do not need bus_i2c_init for DM.
6. struct i2c_parms and struct sram_data are removed.
7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist
   paramter of bus_i2c_init is modified to i2c index. Add new prototype
   i2c_idle_bus and force_bus_idle. Since bus_i2c_init is not good for
   DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus.
   Board file take the responsibility to implement this function, like this:
   "
   int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
   {
	   if (i2c_bus-&gt;index == 0)
		   force_bus_idle(i2c_pads_info0);
	   else if (i2c_bus-&gt;index == 1)
		   force_bus_idle(i2c_pads_info1);
	   else
		   xxxxxx
   }
   "
8. Introduce a weak function, enable_i2c_clk
9. Tested on an i.MX7 platform. Log info:
 =&gt; dm tree
 Class       Probed   Name
 ----------------------------------------
 root        [ + ]    root_driver
 simple_bus  [   ]    |-- soc
 simple_bus  [   ]    |   |-- aips-bus@30000000
 simple_bus  [   ]    |   |   |-- anatop@30360000
 simple_bus  [   ]    |   |   `-- snvs@30370000
 simple_bus  [   ]    |   |-- aips-bus@30400000
 simple_bus  [   ]    |   `-- aips-bus@30800000
 i2c         [   ]    |       |-- i2c@30a20000
 i2c         [   ]    |       `-- i2c@30a40000
 simple_bus  [   ]    `-- regulators
 =&gt; i2c dev 0
 Setting bus to 0
 =&gt; i2c probe
 Valid chip addresses: 08 50
 =&gt; i2c md 8 31
 0031: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's</title>
<updated>2015-04-23T18:56:09Z</updated>
<author>
<name>Sanchayan Maity</name>
<email>maitysanchayan@gmail.com</email>
</author>
<published>2015-04-15T10:54:27Z</published>
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<id>urn:sha1:a94bb7a42c0c377bd4eecc8aec1ef454c9bad51a</id>
<content type='text'>
This driver adds support for the USB peripheral on Freescale Vybrid
SoC's.

Signed-off-by: Sanchayan Maity &lt;maitysanchayan@gmail.com&gt;
</content>
</entry>
<entry>
<title>video, ipu: make ldb clock frequency overwritable through board code</title>
<updated>2015-04-20T07:36:59Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2015-04-20T05:53:48Z</published>
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<id>urn:sha1:cb9f8e6a737e60f460896111b32bbebc45aa1cd1</id>
<content type='text'>
the ldb clock can be setup in board code (for example set through PLL5).
Update the ldb_clock rate also through board code.

This should be removed, if a clock framework is availiable.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Tested-by: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2014-11-05T17:48:09Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-11-05T17:48:09Z</published>
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<id>urn:sha1:625509ab0edbb7d943ad9028de3c21ca48aa58be</id>
<content type='text'>
</content>
</entry>
<entry>
<title>imx: mx6 sabreauto: Add board support for USB EHCI</title>
<updated>2014-11-03T10:21:49Z</updated>
<author>
<name>Ye.Li</name>
<email>B37916@freescale.com</email>
</author>
<published>2014-10-30T10:53:49Z</published>
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<id>urn:sha1:8fe280f330ddfd4a9e395ca15ab4019a1a32aa1f</id>
<content type='text'>
On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.

Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.

The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.

Signed-off-by: Ye.Li &lt;B37916@freescale.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-imx</title>
<updated>2014-10-27T13:08:42Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-10-27T13:08:42Z</published>
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<id>urn:sha1:0ce4af99c07acebf4fce9a91f1099d2460629293</id>
<content type='text'>
</content>
</entry>
<entry>
<title>imx: Add error checking to setup_i2c()</title>
<updated>2014-10-22T16:36:55Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-10-02T01:57:24Z</published>
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<id>urn:sha1:edbf8b4f8c7ef61d3dea5f629e0d756990b8277d</id>
<content type='text'>
Since this function can fail, check its return value.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
</content>
</entry>
<entry>
<title>ARM: i.MX video: declare displays and display_count publicly</title>
<updated>2014-10-21T08:47:14Z</updated>
<author>
<name>Eric Nelson</name>
<email>eric.nelson@boundarydevices.com</email>
</author>
<published>2014-09-30T22:40:04Z</published>
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<id>urn:sha1:a5a9fba42b34f9503e5a496a0c52df18a762abd5</id>
<content type='text'>
Declare displays[] and display_count in imx-common/video.h to
prevent "Should it be static?" messages when compiling board
files with "make C=1".

Signed-off-by: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
</content>
</entry>
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