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<title>u-boot.git/arch/arm/include/asm/imx-common, branch v2017.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/imx-common?h=v2017.01</id>
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<updated>2017-01-02T16:04:38Z</updated>
<entry>
<title>arm: imx: add HAB authentication of image to SPL boot</title>
<updated>2017-01-02T16:04:38Z</updated>
<author>
<name>Sven Ebenfeld</name>
<email>sven.ebenfeld@gmail.com</email>
</author>
<published>2016-11-06T15:37:55Z</published>
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<id>urn:sha1:15b505b0553da2d8a99ae5c1d14968e87f5c6bef</id>
<content type='text'>
When using HAB as secure boot mechanism on Wandboard, the chain of
trust breaks immediately after the SPL. As this is not checking
the authenticity of the loaded image before jumping to it.

The HAB status output will not be implemented in SPL as it adds
a lot of strings that are only required in debug cases. With those
it exceeds the maximum size of the available OCRAM (69 KiB).

The SPL MISC driver support must be enabled, so that the driver can use OTP fuse
to check if HAB is enabled.

Cc: sbabic@denx.de

v2-Changes: None

Signed-off-by: Sven Ebenfeld &lt;sven.ebenfeld@gmail.com&gt;
Reviewed-by: George McCollister &lt;george.mccollister@gmail.com&gt;
Tested-by: George McCollister &lt;george.mccollister@gmail.com&gt;
</content>
</entry>
<entry>
<title>imx-common: lcdif: update lcdif regs for i.MX6SL/SLL</title>
<updated>2016-12-16T10:38:24Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2016-12-11T11:24:34Z</published>
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<id>urn:sha1:003db98ba6bd7cc833bbd79ba28ca1f25e9f3d0e</id>
<content type='text'>
Update lcdif regs for i.MX6SL/SLL

Signed-off-by: Ye.Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: mx6sll: add iomux settings</title>
<updated>2016-12-16T10:38:24Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2016-12-11T11:24:24Z</published>
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<id>urn:sha1:40913fb595d1f909acbe098b3cbb076c8a635dda</id>
<content type='text'>
Add iomux settings for i.MX6 SLL

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Ye.Li &lt;ye.li@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: add i.MX 6SLL CPU type</title>
<updated>2016-12-16T10:38:24Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2016-12-11T11:24:20Z</published>
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<id>urn:sha1:7ce6d3c868407044703f93e315ea3b56fa80f7ff</id>
<content type='text'>
Add i.MX6SLL cpu type.
MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: make ipu's di configurable</title>
<updated>2016-11-29T15:33:21Z</updated>
<author>
<name>Max Krummenacher</name>
<email>max.oss.09@gmail.com</email>
</author>
<published>2016-11-01T14:04:21Z</published>
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<id>urn:sha1:15fde0fc11f93f19f40c9cda36e7c8d4848d9c75</id>
<content type='text'>
The ipu has two display interfaces. Make the used one a parameter
in struct display_info_t instead of using unconditionally DI0.
DI0 is the default setting.

Signed-off-by: Max Krummenacher &lt;max.krummenacher@toradex.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
</content>
</entry>
<entry>
<title>arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support</title>
<updated>2016-10-26T14:53:16Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2016-10-08T12:30:11Z</published>
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<id>urn:sha1:f4b7532f821684010f4c7fcdf64ad1be03b9349d</id>
<content type='text'>
Boot Log for i.CoreM6 DualLite/Solo Starter Kit:
-----------------------------------------------

U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6SOLO rev1.3 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 31C
Reset cause: POR
DRAM:  256 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
** Unable to read file boot.scr **
reading zImage
6741808 bytes read in 341 ms (18.9 MiB/s)
Booting from mmc ...
reading imx6dl-icore.dtb
30600 bytes read in 19 ms (1.5 MiB/s)
   Booting using the fdt blob at 0x18000000
   Using Device Tree in place at 18000000, end 1800a787

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0

Boot Log for i.CoreM6 Quad/Dual Starter Kit:
--------------------------------------------

U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6Q rev1.2 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 28C
Reset cause: POR
DRAM:  512 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
icorem6qdl&gt;

Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Matteo Lisi &lt;matteo.lisi@engicam.com&gt;
Cc: Michael Trimarchi &lt;michael@amarulasolutions.com&gt;
Acked-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>imx-common: enlarge mux width to 4</title>
<updated>2016-10-04T17:37:28Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2016-09-18T08:28:28Z</published>
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<id>urn:sha1:2ee4065571080b96138d9630db2fdcf6990a1289</id>
<content type='text'>
For i.MX6, the mux width is 4, not 3. So enlarge the width.
IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: iomux: fix snvs usage for i.MX6ULL</title>
<updated>2016-10-04T13:41:01Z</updated>
<author>
<name>Peng Fan</name>
<email>van.freenix@gmail.com</email>
</author>
<published>2016-08-11T06:02:51Z</published>
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<id>urn:sha1:07e1c0ae83faff57477392be87734128db5e1b14</id>
<content type='text'>
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.

Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: "Benoît Thébaudeau" &lt;benoit.thebaudeau.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>imx-common: introduce is_mx6ull</title>
<updated>2016-10-04T13:41:00Z</updated>
<author>
<name>Peng Fan</name>
<email>van.freenix@gmail.com</email>
</author>
<published>2016-08-11T06:02:40Z</published>
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<id>urn:sha1:bbd1b07d30548b6829d7bc96a994134fde8e9cb4</id>
<content type='text'>
Introduce is_mx6ull macro.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx-common: introduce simpler macros for runtime dection</title>
<updated>2016-05-24T12:59:55Z</updated>
<author>
<name>Peng Fan</name>
<email>van.freenix@gmail.com</email>
</author>
<published>2016-05-23T10:35:52Z</published>
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<id>urn:sha1:32ff58bb2e1f66aa0fc9d0e9913cdca54eb819a9</id>
<content type='text'>
Introduce simpler macros for runtime cpu dection.

Signed-off-by: Peng Fan &lt;van.freenix@gmail.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
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