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<title>u-boot.git/arch/arm/include/asm/mach-imx, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include/asm/mach-imx?h=master</id>
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<updated>2026-06-27T02:02:46Z</updated>
<entry>
<title>misc: ele_api: Add V2X Get State API</title>
<updated>2026-06-27T02:02:46Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2026-06-26T11:11:52Z</published>
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<id>urn:sha1:00bba5a3587f1b18e8ed8aa67c5dcfca7917dc89</id>
<content type='text'>
Add V2X Get State API to return V2X states for debug purpose

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm: imx8mp: Add new variant parts support</title>
<updated>2026-06-05T12:00:00Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2026-05-22T13:50:15Z</published>
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<id>urn:sha1:dfd83eab76c4ca01732e8782dc815595bd9548fa</id>
<content type='text'>
iMX8MP added 4 new variant parts for low cost industrial and HMI.
The parts disabled HIFI DSP and ISP while other functions are enabled.

Part number:
  - MIMX8ML2DVNLZAB and MIMX8ML2CVNKZAB (2-core)
  - MIMX8ML5DVNLZAB and MIMX8ML5CVNKZAB (4-core)

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx9: Add support for saving DDR training data to NVM</title>
<updated>2026-05-15T20:31:39Z</updated>
<author>
<name>Simona Toaca</name>
<email>simona.toaca@nxp.com</email>
</author>
<published>2026-04-30T08:33:30Z</published>
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<id>urn:sha1:c9a8f673e0b8dc30bd575faae34e0b1f1e42a706</id>
<content type='text'>
DDR training data can be saved to NVM and be available
to OEI at boot time, which will trigger QuickBoot flow.

U-Boot only checks for data integrity (CRC32), while
OEI is in charge of authentication when it tries to
load the data from NVM.

On iMX95 A0/A1, 'authentication' is done via another
CRC32. On the other SoCs, authentication is done by
using ELE to check the MAC stored in the ddrphy_qb_state
structure.

Supported platforms: iMX94, iMX95, iMX952 (using OEI)
Supported storage types: eMMC, SD, SPI flash.

Signed-off-by: Viorel Suman &lt;viorel.suman@nxp.com&gt;
Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Simona Toaca &lt;simona.toaca@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: ahab: Use authenticated header for images loading</title>
<updated>2026-05-15T20:31:39Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2026-04-28T10:09:58Z</published>
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<id>urn:sha1:84a17fea21f8877a668f535145a105db4ccf791e</id>
<content type='text'>
When loading container image, the container header is loaded into
heap memory. If ahab is enabled, the header is be copied to another
fixed RAM for authentication in ahab_auth_cntr_hdr. The better method
is using container header memory being authenticated for following
image loading.
So update ahab_auth_cntr_hdr to return the address of container header
being authenticated. Caller uses this header for following parsing
and image loading.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>misc: ele_api: Add support for XSPI SET GMID command</title>
<updated>2026-03-16T21:44:58Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2026-03-12T00:57:23Z</published>
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<id>urn:sha1:1c6e3a75502062ceb33f06cb4db5e7c5927deac5</id>
<content type='text'>
The XSPI SET GMID command is used to assign GMID ownership to the
requester, allowing access to protected XSPI control registers. This API
must be called in SPL if XSPI GMID-protected settings need to be
modified. Otherwise, XSPI configuration depends on the previous GMID
owner to provide the correct settings.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Alice Guo &lt;alice.guo@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm: imx: Add i.MX952 CPU type support</title>
<updated>2026-03-16T21:44:00Z</updated>
<author>
<name>Alice Guo</name>
<email>alice.guo@nxp.com</email>
</author>
<published>2026-03-02T05:20:05Z</published>
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<id>urn:sha1:14adc4000178ec9069b4b35d87007a0af6e16ca1</id>
<content type='text'>
Add CPU type definition and detection macro for i.MX952 SoC.

Signed-off-by: Alice Guo &lt;alice.guo@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx9: scmi: Get DDR size through SM SCMI API</title>
<updated>2026-03-16T21:44:00Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2026-03-02T05:20:02Z</published>
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<id>urn:sha1:e1cc7117b6302464977fffca3e2c05bf8f3f6c77</id>
<content type='text'>
System Manager(SM) has implemented the MISC protocol to retrieve DDR
information. Using this API, U-Boot can obtain the DDR size dynamically
instead of relying on static configuration macros.

This change addresses the DDR ECC enabled case, where 1/8 of the total
DDR size is reserved for ECC data. The scmi_misc_ddrinfo() returns the
DDR size with EEC overhead already deducted.

Implementation details:
- Query the DDR size via scmi_misc_ddrinfo()
- Replace direct REG_DDR_CS[0,1]_BNDS register reads with SCMI call
- Switch from PHYS_SDRAM[x]_SIZE macros to runtime detection
- For backward compatibility with older SM firmware, fall back to
  static PHYS_SDRAM[x]_SIZE configuration if the SCMI call fails

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Alice Guo &lt;alice.guo@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>misc: ele_api: Add Voltage change start and finish APIs</title>
<updated>2026-01-17T18:00:23Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2026-01-08T11:06:56Z</published>
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<id>urn:sha1:e77d6948f5c2b5fee49b64dbd76bd334219ff963</id>
<content type='text'>
On GDET enabled part, need to call voltage change start and finish
APIs when adjust the voltage more than 100mv. Otherwise GDET will be
triggered and system is reset

Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx9: Add i.MX94 CPU type and SoC-level Kconfig</title>
<updated>2025-09-26T12:51:21Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2025-09-23T02:14:53Z</published>
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<id>urn:sha1:a87b9283266344ac31ef76a3a3ccf2da65429818</id>
<content type='text'>
Introduce support for the new i.MX94 processor, including its CPU type
and SoC-level Kconfig entry.

The i.MX94 is a new member of the i.MX9 family. It uses a System Manager
to handle system-level functions such as power, clock, sensor and pin
control. The System Manager runs on a Cortex-M processor, while the
Cortex-A processor communicates with it via the ARM SCMI protocol and a
messaging unit.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Alice Guo &lt;alice.guo@nxp.com&gt;
Acked-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm: imx: Update ELE get_info structure for i.MX94</title>
<updated>2025-07-17T12:56:33Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2025-07-07T20:42:53Z</published>
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<id>urn:sha1:cadc0abe65ff30d8d5442ec960ca1797920649c4</id>
<content type='text'>
Since i.MX94, the ELE get_info structure is updated to add
OEM PQC SRK hash, so update it.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Signed-off-by: Alice Guo &lt;alice.guo@nxp.com&gt;
Acked-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
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