u-boot.git/arch/arm/include/asm/system.h, branch v2016.01

armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY

2015-11-10T17:03:31+00:00

The implementation of noncached_init() uses define MMU_SECTION_SIZE.
Define this on ARM64.

Move the prototype of noncached_{init,alloc}() to a location that
doesn't depend on !defined(CONFIG_ARM64).

Note that noncached_init() calls mmu_set_region_dcache_behaviour() which
relies on something having set up translation tables with 2MB block size.
The core ARMv8 MMU setup code does not do this by default, but currently
relies on SoC specific MMU setup code. Be aware of this before enabling
this feature on your platform!

Signed-off-by: Stephen Warren

arm: mmu: Add missing volatile for reading SCTLR register

2015-10-16T05:55:51+00:00

Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.

(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163)

Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU  and later causes a PCIE VA access
failure.

Signed-off-by: Alison Wang

armv8: caches: Added routine to set non cacheable region

2015-07-30T23:38:12+00:00

Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.

Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.

Signed-off-by: Siva Durga Prasad Paladugu 
Acked-by: Michal Simek

arm: Add a prototype for save_boot_params_ret()

2015-05-15T00:49:34+00:00

It is convenient for some boards to implement save_boot_params() in C rather
than assembler. Provide a way to return in this case.

Signed-off-by: Simon Glass 
Reviewed-by: Joe Hershberger

tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0

2015-05-13T16:24:15+00:00

These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.

At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine.

So instead I have added a new weak arch function protect_secure_section()
called from relocate_secure_section() and reserved the region there. This is
better overall since it defers the reservation until after the sec vs. non-sec
decision (which can be influenced by an envvar) has been made when booting the
os.

Signed-off-by: Ian Campbell 
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka 
Reviewed-by: Tom Rini 
Reviewed-by: Thierry Reding 
Tested-by: Thierry Reding 
Tested-by: Ian Campbell 
Signed-off-by: Tom Warren

ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching

2015-04-16T12:59:33+00:00

The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those issues.

Signed-off-by: Bryan Brinsko

armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack

2015-02-24T21:08:46+00:00

Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flushing is
completed. Timeout is needed for simualtor on which CCN-504 is not
implemented. Return value can be checked for timeout situation.

Change bootm.c to disable dcache instead of simply flushing, required
by flushing L3.

Signed-off-by: York Sun

arm: Allow lr to be saved by board code

2015-02-16T19:14:54+00:00

The link register value can be required on some boards (e.g. FEL mode on
sunxi) so use a branch instruction to jump to save_boot_params() instead
of a branch link.

This requires a branch back to save_boot_params_ret so adjust the users
to deal with this. For exynos just drop the function since it doesn't
do anything.

Signed-off-by: Simon Glass 
Acked-by: Siarhei Siamashka 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede

ARM: Implement non-cached memory support

2014-12-18T20:19:21+00:00

Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).

The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).

While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.

Signed-off-by: Thierry Reding 
Signed-off-by: Simon Glass 
Signed-off-by: Tom Warren

ARM: cache-cp15: Use more accurate types

2014-11-12T06:25:42+00:00

size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
the system is 64-bit or uses a form of physical address extension to use
a larger address space on 32-bit systems. Using these types the same API
can be implemented on a wider range of systems.

Signed-off-by: Thierry Reding