u-boot.git/arch/arm/include/asm/system.h, branch v2016.09

ARM: Rework and correct barrier definitions

2016-08-05T11:23:57+00:00

As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions.  This was causing a failure to
boot of the Linux kernel.

In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things.  First,  now becomes the source of isb/dsb/dmb
definitions.  This however introduces another complexity.  Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it.  Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier.  The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.

Reviewed-by: Stephen Warren 
Tested-by: Stephen Warren 
Acked-by: Ziyuan Xu 
Acked-by: Sandy Patterson 
Reported-by: Ziyuan Xu 
Reported-by: Sandy Patterson 
Signed-off-by: Tom Rini

arm: implement generic PSCI reset call for armv8

2016-05-27T19:39:46+00:00

Add a psci_system_reset() which calls the SYSTEM_RESET function of
PSCI 0.2 and can be used by boards that support it to implement
reset_cpu().

Signed-off-by: Beniamino Galvani 
Reviewed-by: Simon Glass

arm: Add support for HYP mode and LPAE page tables

2016-03-27T13:12:17+00:00

We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.

So this patch introduces support for both long descriptor PTEs and HYP mode
registers.

Signed-off-by: Alexander Graf

arm64: Add 32bit arm compatible dcache definitions

2016-03-27T13:12:16+00:00

We want to be able to reuse device drivers from 32bit code, so let's add
definitions for all the dcache options that 32bit code has.

While at it, fix up the DCACHE_OFF configuration. That was setting the bits
to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless
bits and make the index explicit.

Signed-off-by: Alexander Graf

arm64: Remove non-full-va map code

2016-03-15T19:13:10+00:00

By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf

arm64: Make full va map code more dynamic

2016-03-15T19:13:01+00:00

The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf

arm: Remove S bit from MMU section entry

2016-01-31T15:32:56+00:00

Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Albert Aribaud 
Cc: Simon Glass

arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7

2016-01-31T15:32:56+00:00

The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured for the
cache on ARMv7 to operate correctly.

The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
issues which are hard to replicate, for example certain USB sticks are not
detected or QSPI NOR sometimes fails to write pages completely.

The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
correct because the code which added the test(s) for CONFIG_ARMV7 was added
shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
not adjusted correctly to reflect that change.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Albert Aribaud 
Cc: Simon Glass

armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure

2016-01-19T22:25:36+00:00

This commit adds functions issuing calls to secure monitor or
hypervisore. This allows using services such as Power State
Coordination Interface (PSCI) provided by firmware, e.g. ARM
Trusted Firmware (ATF)

The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Corey Minyard 
Signed-off-by: Radha Mohan Chintakuntla 
Reviewed-by: Simon Glass 
Tested-by: Mateusz Kulikowski

armv8: New MMU setup code allowing to use 48+ bits PA/VA

2016-01-19T22:25:36+00:00

This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla