u-boot.git/arch/arm/include/asm/system.h, branch v2017.01

ARMv8: Setup PSCI memory and device tree

2016-12-15T19:57:51+00:00

Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.

Signed-off-by: Hongbo Zhang 
Reviewed-by: Tom Rini 
Reviewed-by: York Sun

armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled

2016-11-22T19:40:24+00:00

As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.

Signed-off-by: Alison Wang 
Reviewed-by: York Sun

armv8: Support loading 32-bit OS in AArch32 execution state

2016-11-22T19:40:24+00:00

To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.

The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.

Signed-off-by: Ebony Zhu 
Signed-off-by: Alison Wang 
Signed-off-by: Chenhui Zhao 
Reviewed-by: York Sun

arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-11-13T20:54:36+00:00

While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy 
Reviewed-by: Alexander Graf 
Reviewed-by: Tom Rini

armv8: add hooks for all cache-wide operations

2016-11-07T22:36:29+00:00

SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.

Signed-off-by: Stephen Warren 
Reviewed-by: Simon Glass 
Signed-off-by: Tom Warren

arm: Add PSCI shutdown function

2016-10-18T07:08:08+00:00

Using PSCI you can not only reset the system, you can also shut it down!
This patch exposes a function to do exactly that to whatever code wants
to make use of it.

Signed-off-by: Alexander Graf 
Reviewed-by: Simon Glass

arm: Disable HVC PSCI calls by default

2016-10-18T07:08:08+00:00

All systems that are running on armv8 are running bare metal with firmware
that implements PSCI running in EL3. That means we don't really need to expose
the hypercall variants of them.

This patch leaves the code in, but makes the code explicit enough to have the
compiler optimize it out. With this we don't need to worry about hvc vs smc
calling convention when calling psci helper functions.

Signed-off-by: Alexander Graf 
Reviewed-by: Simon Glass

ARM: Introduce function to switch to hypervisor mode

2016-10-07T00:58:16+00:00

On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.

Cc: beagleboard-x15@googlegroups.com
Signed-off-by: Keerthy 
Reviewed-by: Tom Rini

ARM: Rework and correct barrier definitions

2016-08-05T11:23:57+00:00

As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions.  This was causing a failure to
boot of the Linux kernel.

In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things.  First,  now becomes the source of isb/dsb/dmb
definitions.  This however introduces another complexity.  Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it.  Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier.  The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.

Reviewed-by: Stephen Warren 
Tested-by: Stephen Warren 
Acked-by: Ziyuan Xu 
Acked-by: Sandy Patterson 
Reported-by: Ziyuan Xu 
Reported-by: Sandy Patterson 
Signed-off-by: Tom Rini

arm: implement generic PSCI reset call for armv8

2016-05-27T19:39:46+00:00

Add a psci_system_reset() which calls the SYSTEM_RESET function of
PSCI 0.2 and can be used by boards that support it to implement
reset_cpu().

Signed-off-by: Beniamino Galvani 
Reviewed-by: Simon Glass