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<title>u-boot.git/arch/arm/include/asm/system.h, branch v2018.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A</title>
<updated>2018-05-07T19:53:24+00:00</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2018-04-26T12:51:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=acf1500138bb6b0496fe09d6bffdf8eac3d6ecab'/>
<id>acf1500138bb6b0496fe09d6bffdf8eac3d6ecab</id>
<content type='text'>
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Suggested-by: Alexander Graf &lt;agraf@suse.de&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
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<pre>
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Suggested-by: Alexander Graf &lt;agraf@suse.de&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: make save_boot_params_ret prototype visible for AArch64</title>
<updated>2017-11-21T22:57:22+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-10-10T14:21:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7776cc011df4565ed6cf0be65d33ccf28c2fffab'/>
<id>7776cc011df4565ed6cf0be65d33ccf28c2fffab</id>
<content type='text'>
The save_boot_params_ret() prototype (for those of us, that have a
valid SP on entry and can implement save_boot_params() in C), was
previously only defined for !defined(CONFIG_ARM64).

This moves the declaration to a common block to ensure the prototype
is available to everyone that might need it.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: Andy Yan &lt;andy.yan@rock-chips.com&gt;
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<pre>
The save_boot_params_ret() prototype (for those of us, that have a
valid SP on entry and can implement save_boot_params() in C), was
previously only defined for !defined(CONFIG_ARM64).

This moves the declaration to a common block to ensure the prototype
is available to everyone that might need it.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: Andy Yan &lt;andy.yan@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: layerscape: Enable falcon boot</title>
<updated>2017-10-09T15:48:45+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2017-09-28T15:42:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fb97b8621e6c44e7762bf6f7fd82d1b00519d4fd'/>
<id>fb97b8621e6c44e7762bf6f7fd82d1b00519d4fd</id>
<content type='text'>
Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Łukasz Majewski &lt;lukma@denx.de&gt;
Tested-by: Łukasz Majewski &lt;lukma@denx.de&gt;
</content>
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<pre>
Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Łukasz Majewski &lt;lukma@denx.de&gt;
Tested-by: Łukasz Majewski &lt;lukma@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Support cache invalidate</title>
<updated>2017-05-12T02:03:39+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-04-05T23:53:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6775a8208e3ac60f09b982c2d7b3258e0af86540'/>
<id>6775a8208e3ac60f09b982c2d7b3258e0af86540</id>
<content type='text'>
At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: mmu: Add a function to change mapping attributes</title>
<updated>2017-03-14T15:44:03+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2017-03-06T17:02:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7f9b9f318ff152bd8d2e8b573708e2bdc088c1b1'/>
<id>7f9b9f318ff152bd8d2e8b573708e2bdc088c1b1</id>
<content type='text'>
Function mmu_change_region_attr() is added to change existing mapping
with updated PXN, UXN and memory type. This is a break-before-make
process during which the mapping becomes fault (invalid) before final
attributres are set.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
Function mmu_change_region_attr() is added to change existing mapping
with updated PXN, UXN and memory type. This is a break-before-make
process during which the mapping becomes fault (invalid) before final
attributres are set.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: aarch64: Fix the warning about x1-x3 nonzero issue</title>
<updated>2017-01-18T17:29:33+00:00</updated>
<author>
<name>Alison Wang</name>
<email>b18965@freescale.com</email>
</author>
<published>2017-01-17T01:39:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7c5e1feb1d780cc857632c246e78ac7a8e6cf2d7'/>
<id>7c5e1feb1d780cc857632c246e78ac7a8e6cf2d7</id>
<content type='text'>
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.

Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Tested-by: Ryan Harkin &lt;ryan.harkin@linaro.org&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.

Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Tested-by: Ryan Harkin &lt;ryan.harkin@linaro.org&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARMv8: Setup PSCI memory and device tree</title>
<updated>2016-12-15T19:57:51+00:00</updated>
<author>
<name>macro.wave.z@gmail.com</name>
<email>macro.wave.z@gmail.com</email>
</author>
<published>2016-12-08T03:58:25+00:00</published>
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<id>9a561753ce48def18dbc4aa278c685c93ed0a77d</id>
<content type='text'>
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.

Signed-off-by: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.

Signed-off-by: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled</title>
<updated>2016-11-22T19:40:24+00:00</updated>
<author>
<name>Alison Wang</name>
<email>b18965@freescale.com</email>
</author>
<published>2016-11-10T02:49:05+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3db86f4bbd7a723421c8c9bf9bd09d58e17e9736'/>
<id>3db86f4bbd7a723421c8c9bf9bd09d58e17e9736</id>
<content type='text'>
As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.

Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.

Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: Support loading 32-bit OS in AArch32 execution state</title>
<updated>2016-11-22T19:40:24+00:00</updated>
<author>
<name>Alison Wang</name>
<email>b18965@freescale.com</email>
</author>
<published>2016-11-10T02:49:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ec6617c39741adc6c54952564579e32c3c09c66f'/>
<id>ec6617c39741adc6c54952564579e32c3c09c66f</id>
<content type='text'>
To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.

The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.

Signed-off-by: Ebony Zhu &lt;ebony.zhu@nxp.com&gt;
Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Signed-off-by: Chenhui Zhao &lt;chenhui.zhao@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.

The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.

Signed-off-by: Ebony Zhu &lt;ebony.zhu@nxp.com&gt;
Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Signed-off-by: Chenhui Zhao &lt;chenhui.zhao@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode</title>
<updated>2016-11-13T20:54:36+00:00</updated>
<author>
<name>Keerthy</name>
<email>j-keerthy@ti.com</email>
</author>
<published>2016-10-29T09:49:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=06d43c808d61580d977526deca328e33382b40c8'/>
<id>06d43c808d61580d977526deca328e33382b40c8</id>
<content type='text'>
While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
