u-boot.git/arch/arm/include/asm/system.h, branch v2020.10

arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH

2020-07-29T12:43:40Z

The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel Reviewed-by: Andre Przywara

arm: provide a function for boards init code to modify MMU virtual-physical map

2020-07-10T18:10:43Z

Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski Reviewed-by: Tom Rini

arm: update comments to the common style

2020-07-10T18:10:43Z

Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski Reviewed-by: Tom Rini

arm: use correct argument size of special registers

2020-07-07T22:23:48Z

Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt

ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI

2020-06-02T21:27:04Z

arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada

arm: Don't include common.h in header files

2020-05-18T18:54:24Z

It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass

arm: caches: add DCACHE_DEFAULT_OPTION

2020-05-01T15:34:01Z

Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay

arm: cpu: armv8: add support for arm psci reset2.

2020-01-10T19:18:26Z

Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi Signed-off-by: Vladimir Olovyannikov

psci: Fix warnings when compiling with W=1

2019-07-24T18:15:38Z

This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay

ARMv8: Enable all asynchronous abort exceptions taken to EL3

2018-11-16T18:34:33Z

Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang