u-boot.git/arch/arm/include/asm/system.h, branch v2022.04

Revert most of the series for adding vexpress_aemv8r support

2021-09-03T14:42:15Z

Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits: e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs 30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1 b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant 2f5b7b74903f armv8: Add ARMv8 MPU configuration logic 37a757e227cc armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini

psci: fix double declaration

2021-09-02T15:19:58Z

The prototype of psci_features() duplicated. Remove extra declaration. Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1") Reported-by: Michael Scott Signed-off-by: Oleksandr Suvorov

armv8: Ensure EL1&0 VMSA is enabled

2021-09-02T14:17:45Z

On Armv8-R, the EL1&0 memory system architecture is configurable as a VMSA or PMSA, and resets to an "architecturally unknown" value. Add code to armv8_switch_to_el1_m which detects whether the MSA at EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields. If it is we must ensure the VMSA is enabled so that a rich OS can boot. The MSA and MSA_FRAC fields are described in the Armv8-R architecture profile supplement (section G1.3.7): https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Peter Hoyes

armv8: Disable pointer authentication traps for EL1

2021-09-02T14:17:45Z

The use of ARMv8.3 pointer authentication (PAuth) is governed by fields in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset value of these fields is 'architecturally unknown' so we must ensure that the fields are enabled (to disable the traps) if we are entering the kernel at EL1. The APK field disables PAuth instruction traps and the API field disables PAuth register traps Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer authentication is supported by the hardware. The runtime checks require a second temporary register, so add this to the EL1 transition macro signature and update 2 call sites. Signed-off-by: Peter Hoyes

armv8: Initialize CNTFRQ if at highest exception level

2021-07-23T22:53:46Z

CNTFRQ_EL0 is only writable from the highest supported exception level on the platform. For Armv8-A, this is typically EL3, but technically EL2 and EL3 are optional so it may need to be initialized at EL2 or EL1. For Armv8-R, the highest exception level is always EL2. This patch moves the initialization outside of the switch_el block and uses a new macro branch_if_not_highest_el which dynamically detects whether it is at the highest supported exception level. Linux's docs state that CNTFRQ_EL0 should be initialized by the bootloader. If not set, the the U-Boot prompt countdown hangs. Signed-off-by: Peter Hoyes

arm: remove set_dacr/get_dacr functions

2021-03-02T20:53:37Z

Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel Serie-cc: R Sricharan Signed-off-by: Patrick Delaunay

arm: cosmetic: align TTB_SECT define value

2021-03-02T20:53:37Z

Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay

arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH

2021-03-02T20:53:37Z

The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay

common: board_r: Drop initr_noncached wrapper

2021-01-15T19:36:12Z

Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass

arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH

2020-07-29T12:43:40Z

The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel Reviewed-by: Andre Przywara